TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 356

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DDR
DDR_CTL_24 = 0x80C0
DDR_CTL_25 = 0x80C8
DDR_CTL_26 = 0x80D0
DDR_CTL_27 = 0x80D8
DDR_CTL_28 = 0x80E0
DDR_CTL_29 = 0x80E8
DDR_CTL_30 = 0x80F0
Rev. 3.1 November 1, 2005
Name
-
-
-
-
Name
-
-
-
-
Name
-
-
Name
VERSION
Name
TREF
-
Name
TRAS_MAX
Name
TINIT
Bits
11:0
15:12
Bits
15:0
Bits
15:0
Bits
6:0
7
14:8
15
Bits
6:0
7
14:8
15
Bits
6:0
15:7
Bits
15:0
Default
-
-
-
-
Default
-
-
-
-
Default
-
-
Default
0x2031
Default
0x000
-
Default
0x0000
Default
0x0000
Range
-
-
-
-
Range
-
-
-
-
Range
-
-
Range
0x2031
Range
0x0-0xfff
-
Range
0x0-0xffff
Range
0x0-0xffff
15-26
Description
Reserved
Reserved
Reserved
Reserved
Description
Reserved
Reserved
Reserved
Reserved
Description
Reserved
Reserved
Description
Controller version number
DDR version number of the controller.
READONLY
Description
DRAM TREF parameter in cycles.
Cycles between refresh commands.
Reserved
Description
DRAM TRAS_MAX parameter in cycles.
Maximum Row active time in cycles
Description
DRAM TINIT parameter in cycles.
Initialization time for DDR SDRAM in cycles
Toshiba RISC Processor
TX4939
15
15