TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 357

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DDR
DDR_CTL_31 = 0x80F8
DDR_CTL_32 = 0x8100
DDR_CTL_33 = 0x8108
DDR_CTL_34 = 0x8110
DDR_CTL_35 = 0x8118
DDR_CTL_36 = 0x8120
Rev. 3.1 November 1, 2005
Name
EMRS_DATA
-
Name
OUT_OF_RANGE_ADDR[30:16]
-
Name
TC300C_WR_DQS_SHIFT
-
Name
TC300C_DLL_LOCK
-
Name
TC300C_DQS_OUT_SHIFT
-
Name
OUT_OF_RANGE_ADDR[15:0] 15:0
Bits
13:0
15:14
Bits
8:0
15:9
Bits
8:0
15:9
Bits
8:0
15:9
Bits
Bits
14:0 0x0000
15
Default
0x0000
-
Default
0x0000
Default
0x00
-
Default
0x00
-
Default
0x00
-
Default Range
-
Range
0x0-0xffff Address from command that caused an Out of Range interrupt.
Range
0x0-0x3fff
-
Range
0x0-0x1ff
-
Range
0x0-0x1ff
-
Range
0x0-0x1ff
-
0x0-0x7fff
-
15-27
Description
This is the lower 16 bits of the user address for an out of range request
to the memory devices.
READONLY
Description
Extended mode register data written during initialization or Write
modereg command.
The contents of this register will be loaded into the DRAM during
initialization. Consult the DRAM specification for the correct
settings for this register.
Reserved
Description
Fraction of a cycle to delay the clk_wr signal in the controller.
This parameter controls the amount of delay introduced to the write
datapath to ensure the correct capture of data at the DRAM
interface. It selects the number of 1/360ths of the system clock to
delay the write dq data by to the DRAM.
Reserved
Description
Number of delay elements of TC300C master DLL lock.
The actual number of delay elements of the TC300C macro delay
line used to capture one full clock cycle.
This parameter is automatically updated every 8 clock cycles.
READONLY
Reserved
Description
Fraction of a cycle to delay the write dqs signal to the DRAMs during
writes.
This parameter controls the amount of delay introduced to the write
dqs signal to ensure the correct capture of data at the DRAM
interface. It selects the number of 1/360ths of the system clock to
delay the write dqs by to the DRAM.
Reserved
Description
Address from command that caused an Out of Range interrupt.
This is the upper 15 bits of the user address for an out of range
request to the memory devices.
READONLY
Reserved
Toshiba RISC Processor
TX4939
15
15