TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 364

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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DDR
15.14. DDR Controller Interrupt
An interrupt will be generated when the physical address is out of bounds and the interrupt is unmasked. The external
interrupt will assert when one or both of the following conditions occur:
An address out of bounds occurs when an out of bounds address is detected, and the status register doesn’t indicate that a
previous out of bounds address has been detected and not acknowledged. If another out of bounds address is detected
before the first address out of bounds is acknowledged, then an address out of bounds over-run will occur. Each of these
conditions (interrupt sources) will have a unique mask bit and acknowledge bit in the interrupt mask and interrupt
acknowledge registers. The user can enable none, 1, or both of the conditions (sources) depending on their system
requirements.
Table 15-4 below describes the interrupt control and status parameters in more details.
Out of Range Address, Length and Command Type Registers (out_of_range_addr, out_of_range_length,
out_of_range_type)
These register contain the erroneous address, length and the command type. When multiple interrupts occur before the
initial interrupt is acknowledged, only the initial out of range address and length are saved. Therefore, the 2nd –N th
address and length pairs are lost if the 1st interrupt hasn’t been acknowledged/cleared.
Steps in interrupt generation / acknowledge
When an out of bounds access is detected, the following actions occur:
1) Out of bounds interrupt signal is asserted.
2) The command will enter into the command queue and will execute as normal.
3) The status register will update to indicate an out of range access occurred.
4) The out of range address, length, and command type is saved in the controller register space.
5) The interrupt is cleared when the user writes to the interrupt acknowledge register.
To check for an out of bounds address, the starting address is checked, and the (starting address + length) is checked.
Therefore, even if the instruction starts inbounds, if the length of the transfer puts the access out of bounds, an exception will
occur.
Rev. 3.1 November 1, 2005
Parameter Name
int_status
int_mask
int_ack
address out of bounds (For starting address and/or (starting address+length) out of bounds)
address out of bounds over-run (For starting address and/or (starting address+length) out of bounds)
Description
The first 2 bits describe the interrupt
source, and the 3rd bit is asserted when
any unmasked interrupt occurs.
The interrupt mask register contains
mask bit for each interrupt source.
When the corresponding mask bit is set
to 1, the interrupt is masked (i.e.
disabled).
Similar to the interrupt mask register,
the interrupt acknowledge register
contains acknowledge bits for each
interrupt source. The user can clear a
single interrupt or multiple interrupts
with one write.
Table 15-4 Interrupt Parameter Definition
15-34
Bit 0
Single address out of
range error occurred
Mask single out of
range interrupt
Acknowledge single
address out of range
Bit 1
Multiple address out
of range errors
occurred
Mask multiple out of
range interrupt
Acknowledge
multiple out of range
interrup
Toshiba RISC Processor
Bit 2
(bit0 | bit 1)
Register indicates
that an interrupt has
occurred
Inhibit interrupt pin.
Registers still
function the same ,
but interrupt pin is
never asserted. For
polling systems
None
TX4939
15
15

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