TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 365

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.1. Features
The TX4939 PCI Controller functions as a bus bridge between the TX4939 External PCI (or internal PCI) and the internal
bus (G-Bus).
16.1.1. Overall
16.1.2. Initiator Function
16.1.3. Target Function
Rev. 3.1 November 1, 2005
Compliant to “PCI Local Bus Specification Revision 2.2”
PCI Bus: 32-bit data bus; Internal Bus: 64-bit data bus
Maximum PCI bus clock operating frequency: 66 MHz
Dual address cycle support (40-bit PCI address space)
Supports both the Initiator and Target functions
Supports power management functions that are compliant to PCI Bus Power Management Interface Specifications
Version 1.1.
On-chip PCI Bus Arbiter, can connect to a maximum of six (6) external bus masters
1-channel on-chip DMA Controller (PDMAC) dedicated to the PCI Controller
Supports PCI clock output “enable/disable” mode
The Internal Bus clock and PCI Bus clock are asynchronous and can be set independently
Mounted a retry function on the Internal Bus side also in order to avoid deadlock on the PCI Bus.
Single and Burst transfer from the Internal Bus to the PCI Bus
Supports memory, I/O, configuration, special cycle, and interrupt acknowledge transactions.
Address mapping between the Internal Bus and the PCI Bus can be modified
Mounted 16-stage 64-bit data one FIFO each for Read and Write
Post Write function enables quick termination of a maximum of four Write transactions by the G-Bus without waiting
for completion on the PCI Bus.
Endian switching function
Single and Burst transfer from the PCI Bus to the Internal Bus
Supports memory, I/O, and configuration cycles
Supports high-speed back-to-back transactions on the PCI Bus
Address mapping between the PCI Bus and the Internal bus can be modified
Mounted 16-stage 64-bit data FIFO for Read
Mounted 20-stage 64-bit data FIFO for Write
Post Write function enables quick termination of a maximum of five (5) Write transactions by the PCI Bus without
waiting for completion on the G-Bus.
Read Burst length (pre-fetch data size) on the Internal Bus when reading a pre-fetchable space can be made
programmable
Endian switching function
16-1
Chapter 16. PCI Controller
Toshiba RISC Processor
TX4939
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