TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 371

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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PCIC
16.3.5. On-chip Register
The PCI Controller on-chip register contains the PCI Configuration Space Register and the PCI Controller Control Register.
The registers that can be accessed vary according to whether the current mode is the Host mode or the Satellite mode.
An external PCI Host device only accesses the PCI Configuration Space Register when in the Satellite mode. This register
is defined in the PCI Bus Specifications. A PCI configuration cycle is used to access this register. This register cannot be
accessed when in the Host mode. Section 16.4 “PCI Configuration Space Register” explains each register in detail.
The PCI Controller Control Register is only accessed by the TX49 core and cannot be accessed from the PCI Bus.
Registers in the PCI Controller Control Register that include an offset address in the range from 0xD000 to 0xD07F can only
be accessed when in the Host mode and cannot be accessed when in the Satellite mode. These registers correspond to
PCI Configuration Space Registers that an external PCI Host device accesses when in the Satellite mode. Exceptions to
above access limitations are to address 0xD010, 0xD018, 0xD020 and 0xD024, which correspond to memory 0,1,2, base
address registers and io base register. These four registers are Read/Write accessible in Host mode and Read Only
accessible in satellite mode. Section 16.4 “PCI Controller Control Register” explains each register in detail. Figure 16-4
illustrates the register map when in the Host mode. Figure 16-5 illustrates the register map when in the Satellite mode.
Rev. 3.1 November 1, 2005
0xDFFF
0xD270
0xD000
0xDFFF
0xD270
0xD080
0xD000
G-Bus Address Space
G-Bus Address Space
Control Registers
Control Registers
PCI Controller
PCI Controller
RESERVED
RESERVED
Reserved
Figure 16-5 Register Map (Satellite Mode)
Figure 16-4 Register Map (Host Mode)
16-7
Offsets:
0xD010,0xD018,0x0D20,0xD024 are
accessible as Read Only
0xFF
0x80
0x00
0xFF
0x80
0x00
PCI BUS Configuration Space
PCI BUS Configuration Space
PCI Configuration
Space Register
RESERVED
Toshiba RISC Processor
TX4939
16
16

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