TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 372

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.3.6. Supported PCI Bus Commands
Table 16-3 shows the PCI Bus commands that the PCI Controller supports.
Rev. 3.1 November 1, 2005
I/O Read, I/O Write, Memory Read, Memory Write
This command executes Read/Write access to the address mapped on the G-Bus and PCI Bus.
Memory Read Multiple, Memory Read Line
The Memory Read Multiple command is issued if all of the following conditions are met when the Initiator function
is operating and Burst Read access is issued from the G-Bus to the PCI Bus.
Also, the Read Memory Line command is issued when all of the following conditions are met.
The Memory Read command is issued if these conditions are not met, namely, if “0” is set to the Cache Line Size
field (PCICFG1.CLS) of the PCI Configuration 1 Register. In the case of the target, a normal G-Bus cycle is issued
to the address mapped from the PCI Bus to the G-Bus.
(1) A value other than “0” is set to the Cache Line Size Field (PCICFG1.CLS) of
(2) The Read data word count is larger than the value set in the Cache Line Size Field.
(1) A value other than “0” is set to the Cache Line Size Field (PCICFG1.CLS) of the
(2) The Read data word count is smaller than the value set in the Cache Line Size Field.
Note1:
Note2:
the PCI Configuration 1 Register.
PCI Configuration 1 Register.
C/BE Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
The byte enable signals are asserted as necessary during memory read and
memory write cycles same as I/O Read, I/O Write and Single Access
commands.
asserted.
Host means “supported only at Host mode”.
Satellite means “supported only at Satellite mode”.
Host & Satellite means “supported at both mode”.
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
(Reserved)
(Reserved)
Memory Read (Note 1)
Memory Write (Note 1)
(Reserved)
(Reserved)
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
PCI Command
During burst memory reads, four byte enable signals will be
Table 16-3 Supported PCI Bus Commands
16-8
As Initiator (Note2)
Host & Satellite
Host & Satellite
Host & Satellite
Host & Satellite
Host & Satellite
Host & Satellite
Host & Satellite
Host & Satellite
Host
Host
Host
Host
⎯
⎯
⎯
⎯
As Target (Note2)
Host & Satellite
Host & Satellite
Host & Satellite
Host & Satellite
Host & Satellite
Host & Satellite
Host & Satellite
Host & Satellite
Toshiba RISC Processor
Satellite
Satellite
⎯
⎯
⎯
⎯
⎯
⎯
TX4939
16
16