TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 373

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
Rev. 3.1 November 1, 2005
Memory Write and Invalidate
When the TX4939 operates as the initiator, the PCI Controller issue the Memory Write and Invalidate command if
all of the following conditions are met when write access from the G-Bus to the PCI Bus occurs.
(1) The Memory Write and Invalidate Enable bit (PCISTATUS.MWIEN) of the PCI Status
(2) A value other than “0” was set to the Cache Line Size field (PCICFG1.CLS) of the PCI
(3) The word count of the Write data is larger than the value set in the Cache Line Size field.
When the TX4939 operates as the target, the Memory Write and Invalidate command is converted into G-Bus
Write access.
Note that the TX4939 does not support the cache memory Snoop function.
Dual address cycle
When the TX4939 operates as the initiator, the PCI Controller executes dual access cycles if the PCI Bus address
exceeds 0x00_FFFF_FFFF.
When the TX4939 operates as the target, normal G-Bus cycles are executed to the address mapped from the PCI
Bus to the G-Bus.
Configuration Read, Configuration Write (Only be used by Initiator at Host mode)
The configuration cycles are issued on the PCI Bus by either reading or writing from/to the G2P Configuration Data
Register (G2PCFGDATA) after writing the configuration space address to the G2P Configuration Address Register.
The TX4939 supports both “Type 0” and “Type 1” configuration transactions.
On systems that have PCI card slots, the PCI Host device checks each PCI card slot during system initialization to
see if any PCI device exists, then set the Configuration Space Register of the devices that do exist. If a PCI
Configuration Read operation is performed for devices that do not exist, then by default a Bus Error exception will
be generated since there is no PCI Bus response. Clearing the Bus Error Response During Initiator Read bit
(PCICFG.IRBER) of the PCI Controller Configuration Register makes it possible to execute a Read transaction
without causing a Bus Error. All bits of the data read at this time will be set to “1”.
Accepting Configuration Read and Write (Only be accepted by Target at Satellite mode).
Configuration cycles will be accepted as the target only when in the Satellite mode. After reset, Retry response to
PCI Configuration access will continue until the software sets the Target Configuration Access Ready Bit
(PCICFG.TCAR) of the PCI Controller Configuration Register. Please use the software to set this bit after the
software initialization process ends and the software is ready to accept PCI configuration.
Interrupt Acknowledge
This command issues interrupt acknowledge cycles as an initiator. Interrupt acknowledge cycles are executed on
the PCI Bus when the G2P Interrupt Acknowledge Data Register (G2PINTACK) is read. The value returned by this
Read becomes the interrupt acknowledge cycle data.
The TX4939 does not support interrupt acknowledge cycles as the target.
Special Cycle
This command issues specialy cycles as the initiator. This command issues special cycles on the PCI Bus when
writing to the G2P Special Cycle Data Register (G2PSPC). The written value is output as the special cycle data.
The TX4939 does not support special cycles as the target.
Command Register is set.
Configuration 1 Register.
The Memory Write command is issued if these conditions are not met.
16-9
Toshiba RISC Processor
TX4939
16
16