TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 375

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
It is possible to set each space to valid/invalid or to perform Word Swap (see 16.3.10 “Endian Switching Function). Table
16-5 shows the settings registers for these properties.
When 64-bit access is made to the initiator memory space, two 32-bit Burst accesses are issued on the PCI Bus. 64-bit
access to the I/O space is not supported.
Also, operation is not guaranteed if resources in the PCI space were made cacheable and were then accessed when the
Critical Word First function of the TX49/H4 core was enabled.
Rev. 3.1 November 1, 2005
PCIAddr
PBASE
GBusAddr
Figure 16-7 Address Conversion for Initiator (GBus -> PCI Bus Address Conversion)
Memory Space 0
Memory Space 1
Memory Space 2
I/O Space
GBASE
BusMasterEnable: PCI State Command Register Bus Master Bit (PCISTATUS.BM)
39
39
AM
35
35
35
000
Table 16-5 Initiator Access Space Properties Register
BusMasterEnable & PCICCFG.G2PM0EN
BusMasterEnable & PCICCFG.G2PM1EN
BusMasterEnable & PCICCFG.G2PM2EN
BusMasterEnable & PCICCFG.G2PIOEN
Compare
- - - - -
000
Enable
16-11
111
- - - - - -
G2PM0GBASE.BSWAP,
G2PM0GBASE.EXFER
G2PM1GBASE.BSWAP,
G2PM1GBASE.EXFER
G2PM2GBASE.BSWAP,
G2PM2GBASE.EXFER
G2PIOGBASE.BSWAP,
G2PIOGBASE.EXFER
Endian Swap
111
Toshiba RISC Processor
8
8
8
7
7
7
0x00
0x00
0x00
0
0
0
0
0
TX4939
Rev 1.00
16
16