TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 381

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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PCIC
16.3.13. PDMAC (PCI DMA Controller)
The PCI DMA Controller (PDMAC) is a one-channel PCI Director Memory Access (DMA) controller. Data can be transferred
bidirectionally between the G-Bus and the PCI Bus.
Note:
controllers on the G-Bus.
16.3.13.1. Simple (Non-Chain) DMA Transfer
The steps to follow for a non-chain DMA transfer mode are described below.
Rev. 3.1 November 1, 2005
The PDMAC can only access the DDR controller on the G-Bus. It does not provide support for access to other
(1)
(2)
(3)
(4)
(5)
(6)
Address Register and Count Register Setting
Set values for the following three registers.
Chain Address Register Setting
Set “0” to the PDMAC Chain Address Register (PDMCA).
PDMAC Status Register (PDMSTATUS) Clearing
Clear any remaining status from a previous DMA transfer.
PDMAC Control register (PDMCFG) Setting
Clear the Channel Reset bit (CHRST), and make settings such as the data transfer
direction (XFRDIRC), and the data transfer unit size (XFRSIZE).
DMA Transfer Initiation
Set the Transfer Active bit (XFRACT) of the PDMAC Control Register initiates DMA
transfer.
Termination Report
When the DMA data transfer terminates normally, the Normal Data Transfer Completion
bit (NTCMP) of the PDMAC Status Register (PDMSTATUS) is set. An interrupt is then
reported if the Normal Data Transfer Complete Interrupt Enable bit (NTCMPIE) of the
PDMAC Control Register is set.
If an error is detected during DMA transfer, the error cause is recorded in the lower 5 bits
of the PDMAC Status Register and the transfer is aborted. An interrupt is then reported if
the Error Detection Interrupt Enable bit (ERRIE) of the PDMAC Control register is set.
□ PDMAC G-Bus Address Register (PDMGA)
□ PDMAC PCI Bus Address Register (PDMPA)
□ PDMAC Count Register (PDMCTR)
16-17
Toshiba RISC Processor
TX4939
16
16

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