TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 382

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.3.13.2. Chain DMA
DMA Command Descriptors are 4 QWORD (32-Byte) data structures indicated in Table 16-9 that are placed in memory.
Storing the starting memory address of another DMA Command Descriptor in the Offset 0 Chain Address Field makes it
possible to configure a chain list for the DMA command Descriptor. Set “0” in the Chain Address field of the DMA Command
Descriptor at the end of the chain list.
When the DMA transfer specified by one DMA Command Descriptor ends, the PDMAC reads the next DMA Command
Descriptor that the Chain Address field automatically points to, then continues the DMA transfer. Such continuous DMA
transfer that uses multiple descriptors in a chain format is referred to as the Chain DMA mode.
When a DMA Command Descriptor is placed to an address that does not extend across a 32 QWORD boundary in memory,
this transfer method is more efficient since data can be read by a single G-Bus Burst Read transaction.
The DMA transfer procedure is as follows when in the Chain DMA mode.
Rev. 3.1 November 1, 2005
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Count Register Setting
Sets “0” to the PDMAC Count Register (PMDCTR).
DMA Command Descriptor Chain Construction
Constructs the DMA Command Descriptor Chain in memory.
PDMAC Status Register (PDMSTATUS) Clearing
Clears any remaining status from a previous DMA transfer.
PDMAC Control Register (PDMCFG) Setting
Clears the Channel Regster bit (CHRST) and makes settings such as the data transfer direction
(XFRDIRC) and the data transfer unit size (XFRSIZE).
DMA Transfer Initiation
Setting the address of the DMA Command descriptor that is at the beginning of the Chain List in the
PDMAC Chain Address Register (PDMCA) automatically initiates DMA transfer.
First, the values stored in each field of the DMA Command Descriptor that is at the beginning of the
Chain List are read to each corresponding PDMAC Register, then DMA transfer is performed
according to the read values.
If a value other than “0” is stored in the PDMAC Chain Address Register (PDMCA), data transfer of
the size stored in the PDMAC Count Register is complete, then the DMA Command Descriptor value
for the memory address specified by the PDMAC Chain Address Register is read.
When the Chain Address field value reads a descriptor of “0”, the PDMAC Chain Address Register
value is not updated and the previous value (address of the Data Command Descriptor at which the
Chain Address field value is “0” when read) is held.
0 value judgement is performed when the lower 32 bits of the PDMAC Chain Address Register are
rewritten. DMA transfer is automatically initiated if the value was not “0”. Therefore, please write to the
upper 32 bits first when writing to the PDMAC Chain Address Register using a 32-bit Store instruction.
Termination Report
When DMA data transfer of all descriptor chains terminates normally, the Normal Chain Complete bit
(NCCMP) of the PDMAC Status Register is set. An interrupt is reported if the Chain Termination
Interrupt Enable bit (MCCMPIE) of the PDMAC Control register (PDMCFG) is set.
Also, the Normal Data Transfer Complete bit (NTCMP) of the DPMAC Status Register is set each
time the DMA data transfer specified by a DMA Command Descriptor terminates normally. An
interrupt is reported if the Normal Data Transfer Complete Interrupt Enable bit (NTCMPIE) of the
PDMAC Control Register (PDMCFG) is set.
If an error is detected during DMA transfer, the error cause is recorded in the lower 5 bits of the
PDMAC Status Register and the transfer is aborted. An interrupt is then reported if the Error Detection
Interrupt Enable bit (ERRIE) of the PDMAC Control register is set.
Offset Address
0x00
0x08
0x10
0x18
Field Name
Chain Address
G-Bus Address
PCI Bus Address
Count
Table 16-9 DMA Command Descriptors
16-18
Transfer Destination Register
PDMAC Chain Address Register (PDMCA)
PDMAC G-Bus Address Register (PDMGA)
PDMAC PCI Bus Address Register (PDMPA)
PDMAC Count Register (PDMCTR)
Toshiba RISC Processor
TX4939
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