TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 386

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.3.15.2. Priority Control
As illustrated below in Figure 16-13, a combination of two round-robin sequences is used as the arbitration algorithm that
determines the priority of Internal PCI Bus arbiter bus requests. The round-robin with the lower priority (Level 2) consists of
Masters W - Z, and the round-robin with the high priority (Level 1), consists of Master A - D. The PCI Bus Arbiter Request
Port Register (PBAREQPORT) specifies whether to allocate the PCI Controller and the six External Bus Masters to Masters
A - D or W - Z.
The Bus Master priority is determined based on the Level 1 round-robin sequence. However, when Level 2 is used inside
Level 1, the Level 2 Bus Master priority is determined based on the Level 2 round-robin sequence.
All 8 Bus Masters cannot be used on the TX4939. However, the Bus Master priority would be as follows if we assume there
is a hypothetical device that can use all 8 Bus Masters and all 8 Bus Masters (Masters A – D, W – Z) simultaneously
requested the bus.
Since the priority can only transition in the order indicated by the above arrows (or the arrows in Figure 16-13, if we assume
that the three Bus Masters A, B, and W exist, then Master B will obtain the bus first. If A and W then simultaneously request
the bus, then PCI Bus ownership will transition in the order B → W → A.
Rev. 3.1 November 1, 2005
Level 2
(Priority Low)
Level 1
(Priority High)
Master
Figure 16-13 PCI Bus Arbitration Priority
Master
Z
A
Master
→ A → B → C → D → X
→ A → B → C → D → Y
→ A → B → C → D → Z
→ A (returns to the beginning)
→ A → B → C → D → W
B
16-22
Level 2
Master
Master
W
Y
Master
C
Master
Master
D
X
Toshiba RISC Processor
TX4939
16
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