TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 387

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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PCIC
16.3.15.3. Bus Parking
The On-chip PCI Bus Arbiter supports bus parking.
The last PCI Bus Master is made the Park Master when the Fix Park Master bit (FIXPM) of the PCI Bus Arbiter Configuration
Register (PBACFG) is cleared (in the default state). When this bit is set, the Internal PCI Bus Arbiter Request A Port (Master
A) becomes the Park Master.
16.3.15.4. Broken Master Detect
The TX4939 On-chip PCI Bus Arbiter has a function for automatically detecting broken masters.
If the PCI Bus Master requests and is granted the bus when the PCI Bus is in the Idle state, this master must assert the
FRAME* signal within 16 PCI block cycles and start a transaction. The PCI Bus Arbiter recognizes any device that breaks
this rule as a broken bus master and removes that device from the bus arbitration sequence.
This detection function is enabled when the Broken Master Check Enable bit (BMCEN) of the PCI Bus Arbiter Configuration
Register (PBACFG) is set. When a broken master is detected, the Broken Master Detection bit (PBSTATUS.BMD) of the
PCI Bus Arbiter Status Register is set and the bit in the PCI Bus Arbiter Broken Master Register (PBABM) that corresponds
to that master is set. Then it also becomes possible to report an interrupt.
16.3.15.5. Special Programming
There may be some devices among PCI bus masters that operate differently from typical PCI devices. PCI devices with the
following characteristics can be made usable by changing the programming of the PCI bus arbiter.
For example, a bus master with both of the above characteristics can be used by configuring the PCI bus arbiter as follows:
If this bus master is connected to REQ[3] and broken master checking is to be enabled, values to be written to the PBACFG
and PBAREQPORT registers are as follows:
Rev. 3.1 November 1, 2005
(1)
(2)
□ Set the internal PCI bus arbiter to the fixed parked master.
□ Assign the TX4939 to request port A.
□ Assign the bus master to request port B.
PBACFG (at 0xD104):
PBAREQPORT (at 0xD100):
Bus masters that can not re-assert REQ unless GNT is once deasserted after deasserting REQ
Bus masters that initiate a PCI transaction even when the deassertion of GNT has taken away
their bus mastership before the start of the transaction
□ Assign the bus master to a request port other than Port A through the
□ Enable the Fixed Parked Master (FIXPA) bit in the PBACFG register (at
□ Assign the bus master to request port A, B, C or D through the PBAREQPORT
PBAREQPORT register (at 0xD100). (Assign the TX4939 to Port A.)
0xD104).
register (at 0xD100).
0x0000000B
0x73546210
16-23
Toshiba RISC Processor
TX4939
16
16

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