TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 392

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.4.2. PCI Status, Command Register (PCISTATUS)
The upper 16 bits correspond to the Status Register in the PCI Configuration Space, and the lower 16 bits correspond to the
Command Register in the PCI Configuration Space.
Rev. 3.1 November 1, 2005
Bit
31
30
29
28
27
26:25
24
23
Default
Default
NAME
NAME
TYPE
TYPE
Mnemonic
DPE
SSE
RMA
RTA
STA
DT
MDPE
FBBCP
R/W1C R/W1C R/W1C R/W1C R/W1C
DPE
31
15
0
SSE
30
14
0
Field Name
Detected Parity
Error
Signaled System
Error
Received Master
Abort
Received Target
Abort
Signaled Target
Abort
DEVSEL Timing
Master Data Parity
Error
Fast Back-to-Back
Capable
RMA
29
13
Reserved
0
RTA
28
12
0
Figure 16-15 PCI Status, Command Register
Table 16-15 PCI Status, Command Register
STA
27
11
0
Description
Detected Parity Error (Default: 0)
Indicates that a parity error was detected. A parity error is detected in the
three following situtations:
Detected a data parity error as the Read command PCI initiator.
Detected a data parity error as the Write command PCI target.
Detected an address parity error.
This bit is set regardless of the setting of the Parity Error Response bit
(PCISTATUS.PEREN) of the PCI Status, Command Register.
1: Detected a parity error.
0: Did not detect a parity error.
Signaled System Error (Default: 0)
Detects either an address parity error or a special cycle data parity error. This
bit is set when the SERR* signal is asserted.
1: Asserted the SERR* signal
0: Did not assert the SERR* signal.
Received Master Abort (Default: 0)
This bit is set when a Master Abort aborts a PCI Bus Transaction when the
PCI Controller operates as the PCI initiator (except for special cycles).
1: Transaction was aborted by a Master Abort.
0: Transaction was not aborted by a Master Abort.
Received Target Abort (Default: 0)
This bit is set when a Target Abort aborts a PCI Bus Transaction when the
PCI Controller operates as the PCI initiator.
1: Transaction was aborted by a Target Abort.
0: Transaction was not aborted by a Target Abort.
Signaled Target Abort (Default: 0)
This bit is set when a Target Abort aborts a PCI Bus Transaction when the
PCI Controller operates as the PCI target.
1: Bus transaction was aborted by a Target Abort.
0: Bus transaction was not aborted by a Target Abort.
DEVSEL Timing (Fixed Value: 01)
Three DEVSEL assert timings are defined in the PCI 2.2 Specifications: 00b
= Fast; 01b = Medium; 10b = Slow; 11b = Reserved).
With the exception of Read Configuration and Write Configuration, when the
PCI Controller is the PCI target, the DEVSEL signal is asserted to a certain
bus command and indicates the slowest speed for responding to the PCI
Bus Master.
Master Data Parity Error (Default: 0)
Indicates the a parity error occurred when the PCI Controller is the PCI
initiator. This bit is not set when the PCI Controller is the target.
This bit is set when all of the three following conditions are met.
It has been detected that the PERR* signal was set either directly or
indirectly.
The PCI Controller is the Bus Master for a PCI Bus transaction during which
an error occurred.
The Parity Error Response bit of the PCI Status Command Register
(PCISTATUS.PEREN) has been set.
Fast Back-to-Back Capable (Fixed Value: 1)
Indicates whether target access of a fast back-to-back transaction can be
accepted. Is fixed to “1”.
26
10
DT
01
R
FBBEN SEREN STPC PEREN VPS MWIEN
R/W
25
9
0
16-28
R/W1C
MDPE FBBCP
R/W
24
0
8
0
23
R
R
1
7
0
R/W
Rsvd
22
6
0
66MCP
21
R
R
1
5
0
R/W
CL
20
R
Toshiba RISC Processor
1
4
0
SC
19
3
R
0
R/W
BM
0/1
18
Reserved
2
MEMSP IOSP
R/W
17
1
0
TX4939
R/W
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R
R/W1C
R
R/W
16
0
0
16
16