TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 393

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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PCIC
Rev. 3.1 November 1, 2005
Bit
22
21
20
19:10
9
8
7
6
5
4
3
2
1
0
Mnemonic
66MCP
CL
FBBEN
SEREN
STPC
PEREN
VPS
MWIEN
SC
BM
MEMSP
IOSP
Field Name
Reserved
66 MHz Capable
Capabilities List
Reserved
Fast Back-to-Back
Enable
SERR* Enable
Stepping Control
Parity Error
Response
VGA Palette
Snoop
Memory Write and
Invalidate Enable
Special Cycles
Bus Master
Memory Space
I/O Space
Table 16-15 PCI Status, Command Register
Description
66 MHz Capable (Fixed Value: 1)
Indicates the 66 MHz operation is possible. Is fixed to “1”.
Capabilities List (Fixed Value: 1)
Indicates that the capabilities list is being implemented. Is fixed to “1”.
Fast Back-to-Back Enable (Default: 0)
Indicates that issuing of fast back-to-back transactions has been enabled.
1: Enable
0: Disable
SERR* Enable (Default: 0)
Enables/Disables the SERR* signal.
The SERR* signal reports that either a PCI Bus address parity error or a
special cycle data parity error was detected. The SERR* signal is only
asserted when the Parity Error Response bit is set and this bit is set.
1: Enable
0: Disable
Stepping Control (Fixed Value: 0)
Indicates that stepping control is not being supported.
Parity Error Response (Default 0)
Sets operation when a PCI address/data parity error is detected.
A parity error response (either when the Parity Error Response bit
(PCISTATUS.PEREN) of the PERR* Signal Assert or PCI Status, Command
Register is set, or the SERR* signal is asserted) is performed only when this
bit is set.
When this bit is cleared, the PCI Controller ignores all parity errors and
continues the transaction process as if the parity of that transaction was
correct.
1: Parity error response is performed.
0: Parity error response is not performed.
VGA Palette Snoop (Fixed Value: 0)
Indicates that the VGA palette snoop function is not supported.
Memory Write and Invalidate Enable (Default: 0)
Controls whether to use the Memory Write and Invalidate command instead
of the Memory Write command when the PCI Controller is the initiator.
Special Cycles (Fixed Value: 0)
Indicates that special cycles will not be accepted as PCI targets.
Bus Master (Default: 0/1)
The default is only “1” when in the Host mode.
1: Operates as the Bus Master.
0: Does not operate as the Bus Master.
Memory Space (Default: 0)
1: Respond to PCI memory access.
0: Do not respond to PCI memory access.
I/O Space (Default: 0)
1: Respond to PCI I/O access.
0: Do not respond to PCI I/O access.
16-29
Toshiba RISC Processor
TX4939
R/W
R
R
R/W
R/W
R
R/W
R
R/W
R
R/W
R/W
R/W
16
16

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