TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 398

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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PCIC
16.4.7. P2G Memory Space 0 PCI Upper Base Address Register
This register is unused since the PCI Controller does not support the target dual-address cycle. It is forbidden to write to this
register.
16.4.8. P2G Memory Space 1 PCI Upper Base Address Register
This register is unused since the PCI Controller does not support the target dual-address cycle. It is forbidden to write to this
register.
16.4.9. P2G I/O Space PCI Base Address Register (P2GIOPBASE)
This register corresponds to the I/O Space Base Address at offset address 0x24 of the PCI Configuration Space.
In case of Satellite Mode, this register will be read only.
Rev. 3.1 November 1, 2005
Default
Default
NAME
NAME
Bit
31:8
7:1
0
TYPE
TYPE
Mnemonic
BA[31:8]
IOSI
31
15
30
14
Field Name
Base Address
Reserved
I/O Space
29
13
(P2GM0PUBASE)
(P2GM1PUBASE)
Figure 16-20 P2G I/O Space PCI Base Address Register
Table 16-21 P2G I/O Space PCI Base Address Register
28
12
BA[15:8]
0x00
R/W
27
11
Description
Base Address (Default: 0x00)
Sets the PCI base address of the Target Access I/O Space. The size of this
I/O space is fixed at 256 Bytes.
In Satellite Mode, this field will be read only.
I/O Space Indicator (Fixed Value: 1)
1: Indicates that this Base Address Register is for use by the PCI I/O Space.
26
10
25
9
16-34
R/W or R/O
24
BA[31:16]
8
0x0000
23
7
22
6
21
5
Reserved
20
Toshiba RISC Processor
4
19
3
18
2
17
1
R/W
R/W
R/O
R
TX4939
or
IOSI
16
R
0
1
16
16

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