TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 406

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.4.19. P2G Status Register (P2GSTATUS)
Rev. 3.1 November 1, 2005
Bit
31:25
24
23
22
21
20
19
18
17
16:0
Default
Default
NAME
NAME
TYPE
TYPE
Mnemonic
PMSC
PMEES
PMECLR
M66EN
IOBFE
IIBFE
TOBFE
TIBFE
31
15
30
14
Field Name
Reserved
PM State Change
Detected
PME_En Set
Detected
PME Status Clear
Detected
66 MHz Drive
Status
Initiator
Out-Bound FIFO
Empty
Initiator In-Bound
FIFO Empty
Target Out-Bound
FIFO Empty
Target In-Bound
FIFO Empty
Reserved
29
13
28
12
27
11
Description
Power Management State Change (Default: 0x0)
This bit is not valid in the TX4939.
“1” is set to this bit when the PowerState field of the Power Management
Register (PMCSR) is rewritten.
This bit is cleared to “0” when a “1” is written to it.
PME_En Set (Default: 0x0)
This bit is not valid in the TX4939.
This bit is set to “1” when the PME_En bit of the PMCSR Register is set to “1”.
When this bit is set, it indicates that the PCI Master (Host) device enabled
PME* signal output.
1: Indicates that the PME_En bit is set.
0: Indicates that the PME_En bit is not set.
This bit is cleared to “0” when a “1” is written to it.
PME_Status Clear (Default: 0x0)
This bit is not valid in the TX4939.
This bit indicates that the PME_Status bit of the PMCSR Register was
cleared.
1: Indicates that the PME_Status bit was cleared.
0: Indicates that the PME_Status bit was not cleared.
This bit is cleared to “0” when a “1” is written to it.
M66EN Status (Default: 0x0)
This bit indicates the current status of the M66EN signal. This bit can only be
read. Writes to this bit are invalid.
1: The M66EN signal is asserted.
0: The M66EN signal is deasserted.
Initiator Out-Bound FIFO Empty (Default: 0x1)
1: Indicates that the Initiator Out-Bound FIFO is empty.
0: Indicates that the Initiator Out-Bound FIFO is not empty.
This is a diagnostic function.
Initiator In-Bound FIFO Empty (Default: 0x1)
1: Indicates that the Initiator In-Bound FIFO is empty.
0: Indicates that the Initiator In-Bound FIFO is not empty.
This is a diagnostic function.
Target Out-Bound FIFO Empty (Default: 0x1)
1: Indicates that the Target Out-Bound FIFO is empty.
0: Indicates that the Target Out-Bound FIFO is not empty.
This is a diagnostic function.
Target In-Bound FIFO Empty (Default: 0x1)
1: Indicates that the Target In-Bound FIFO is empty.
0: Indicates that the Target In-Bound FIFO is not empty.
This is a diagnostic function.
Figure 16-30 P2G Status Register
Table 16-31 P2G Status Register
26
10
25
9
16-42
R/W1C R/W1C R/W1C
PMSC
RESERVED
0x0
24
8
PMEES
0x0
23
7
PMECLR
0x0
22
6
M66EN IOBFE IIBFE TOBFE TIBFE Rsvd
0x0
21
R
5
0x1
20
R
Toshiba RISC Processor
4
0x1
19
R
3
0x1
18
R
2
0x1
17
R
1
R/W
⎯
R/W1C
R/W1C
R/W1C
R
R
R
R
R
⎯
TX4939
16
0
16
16