TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 410

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.4.23. PCI Bus Arbiter Configuration Register (PBACFG)
This register is only valid when using the on-chip PCI Bus Arbiter.
Rev. 3.1 November 1, 2005
Bit
31:4
3
2
1
0
Default
Default
NAME
NAME
TYPE
TYPE
Mnemonic
FIXPA
RPBA
PBAEN
BMCEN
31
15
30
14
Field Name
Rsvd
Fixed Park Master Fixed Park Master (Default: 0)
Reset PCI Bus
Arbiter
PCI Bus Arbiter
Enable
Broken Master
Check Enable
29
13
Figure 16-34 PCI Bus Arbiter Configuration Register
Table 16-35 PCI Bus Arbiter Configuration Register
28
12
27
11
Description
Selects the method for determining the Park Master.
0: The last Bus Master becomes the Park Master.
1: Internal PCI Bus Arbiter Request Port A is the Park Master.
Reset PCI Bus Arbiter (Default: 0)
Resets the PCI Bus Arbiter. However, the PCI Bus Arbiter Register settings
are saved. Please use the software to clear this bit.
1: The PCI Bus Arbiter is currently being reset.
0: The PCI Bus Arbiter is not currently being reset.
PCI Bus Arbiter Enable (Default: 0)
This is the Bus Arbiter Enable bit. After Reset, External PCI Bus requests to
the PCI Arbiter cannot be accepted until this bit is set to “1”. The PCI
Controller is the default Parking Master after Reset.
1: Enables the PCI Bus Arbiter.
0: Disables the PCI Bus Arbiter.
Broken Master Check Enable (Default: 0)
Controls Broken Master detection.
1: Enables the Broken PCI Bus Master check.
0: Disables the Broken PCI Bus Master check.
RESERVED
26
10
25
9
16-46
RESERVED
24
8
23
7
22
6
21
5
20
Toshiba RISC Processor
4
FIXPA RPBA PBAEN
R/W
19
3
0
R/W
18
2
0
R/W
17
1
0
R/W
⎯
R/W
R/W
R/W
R/W
TX4939
BMCEN
R/W
16
0
0
16
16