TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 427

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.4.43. PCI Controller Status Register (PCICSTATUS)
Rev. 3.1 November 1, 2005
Default
Default
NAME
NAME
Bit
31:11
10
9
8
7
6
5
4
3
2
1
TYPE
TYPE
Mnemonic
PME
TLB
NIB
ZIB
PERR
SERR
GBE
IWB
31
15
30
14
RESERVED
Field Name
Rsvd
PME Detect
Long Burst
Transfer Detect
Negative
Increment Burst
Detect
Zero Increment
Burst Detect
Rsvd
PERR* Detected
SERR* Detected
G-Bus Error
Detect
Rsvd
Initiator Write
Busy
29
13
28
12
Table 16-55 PCI Controller Status Register
Figure 16-54 PCI Controller Status Register
27
11
Description
PME Detect (Default: 0x0)
This bit indicates that assertion of the PME* signal was detected.
1: Indicates that assertion of the PME* signal was detected.
0: Indicates that assertion of the PME* signal was not detected.
Too Long Burst Detect (Default: 0x0)
Indicates that a Burst transfer by the on-chip DMA Controller exceeding 16
DWORDs was detected.
1: Indicates that a Burst transfer exceeding 16 DWORDs was detected.
0: Indicates that no Burst transfer exceeding 16 DWORDs was detected.
Negative Increment Burst Detect (Default: 0x0)
Indicates that Burst transfer by the on-chip DMA Controller in the negative
direction was detected.
1: Indicates that a Burst transfer in the negative direction was detected.
0: Indicates that no Burst transfer in the negative direction was detected.
Zero Increment Burst Detect (Default: 0x0)
Indicates that Burst transfer by the on-chip DMA Controller without an
address increment was detected.
1:
detected.
0:
detected.
PERR* Occurred (Default: 0x0)
Indicates that the Parity Error signal (PERR*) was asserted. This bit is a
monitor status bit that records assertion of the PERR* signal even if the
TX4939 is not accessing PCI.
1: Indicates that the PERR* signal was asserted.
0: Indicates that the PERR* signal was not asserted.
SERR* Occurred (Default: 0x0)
Indicates that the System Error signal (SERR*) was asserted. This bit is a
monitor status bit that records assertion of the SERR* signal even if the
TX4939 is not accessing PCI.
1: Indicates that the SERR* signal was asserted.
0: Indicates that the SERR* signal was not asserted.
G-Bus Error Detect (Default: 0x0)
Indicates that a G-Bus Error occurred in the G-Bus Master cycle of the PCI
Controller. This error is indicated when a timeout occurs on the G-Bus. This
bit is only set by Master cycle Bus Errors.
1: Indicates that a G-Bus Error was detected.
0: Indicates that no G-Bus Error was detected.
Initiator Write Busy (Busy: 0x0)
Indicates that a Write cycle was in progress when a Write cycle to the PCI Bus
was executed.
While a Write cycle is in progress, no error status to that Write cycle is
reflected. Therefore, this bit is used to confirm the status when it changes
from “1” to “0” after the Write cycle ends.
1: Indicates that a Write cycle is in progress.
0: Indicates that no Write cycle is in progress.
R/W1C R/W1C R/W1C R/W1C
PME
0x0
26
10
Indicates that a Burst transfer without an address increment was
Indicates that no Burst transfer without an address increment was
TLB
0x0
25
9
16-63
RESERVED
NIB
0x0
24
8
ZIB
0x0
23
7
Rsvd PERR SERR GBE
22
6
R/W1C R/W1C R/W1C
0x0
21
5
0x0
20
Toshiba RISC Processor
4
0x0
19
3
Rsvd
18
2
IWB E2PDONE
0x0
17
R
1
R/W
⎯
R/W1C
R/W1C
R/W1C
R/W1C
⎯
R/W1C
R/W1C
R/W1C
⎯
R
TX4939
16
⎯
R
0
16
16