TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 43

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

3.3.5
3.3.6
3.3.7
CMOS logic IC inputs, for example, have extremely high impedance. If an input pin is left open, it can easily
pick up extraneous noise and become unstable. In this case, if the input voltage level reaches an intermediate
level, it is possible that both the P-channel and N-channel transistors will be turned on, allowing unwanted
supply current to flow. Therefore, ensure that the unused input pins of a device are connected to the power
supply (Vcc) pin or ground (GND) pin of the same device. For details of what to do with the pins of heat sinks,
refer to the relevant technical datasheet and databook.
Latch-up is an abnormal condition inherent in CMOS devices, in which Vcc gets shorted to ground. This
happens when a parasitic PN-PN junction (thyristor structure) internal to the CMOS chip is turned on, causing a
large current of the order of several hundred mA or more to flow between Vcc and GND, eventually causing the
device to break down.
Latch-up occurs when the input or output voltage exceeds the rated value, causing a large current to flow in the
internal chip, or when the voltage on the Vcc (Vdd) pin exceeds its rated value, forcing the internal chip into a
breakdown condition. Once the chip falls into the latch-up state, even though the excess voltage may have been
applied only for an instant, the large current continues to flow between Vcc (Vdd) and GND (Vss). This causes
the device to heat up and, in extreme cases, to emit gas fumes as well. To avoid this problem, observe the
following precautions:
(1) Do not allow voltage levels on the input and output pins either to rise above Vcc (Vdd) or to fall below
(2) Do not allow any abnormal noise signals to be applied to the device.
(3) Set the voltage levels of unused input pins to Vcc (Vdd) or GND (Vss).
(4) Do not connect output pins to one another.
Wired-AND configurations, in which outputs are connected together, cannot be used, since this short-circuits the
outputs. Outputs should, of course, never be connected to Vcc (Vdd) or GND (Vss).
Furthermore, ICs with tri-state outputs can undergo performance degradation if a shorted output current is
allowed to flow for an extended period of time. Therefore, when designing circuits, make sure that tri-state
outputs will not be enabled simultaneously.
Some devices display increased delay times if the load capacitance is large. Also, large charging and discharging
currents will flow in the device, causing noise. Furthermore, since outputs are shorted for a relatively long time,
wiring can become fused.
Consult the technical information for the device being used to determine the recommended load capacitance.
Latch-up
GND (Vss). Also, follow any prescribed power-on sequence, so that power is applied gradually or in steps
rather than abruptly.
Input/Output protection
Load capacitance
3 General Safety Precautions and Usage Considerations
3-7