TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 435

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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PCIC
16.4.50. G2P Configuration Data Register (G2PCFGDATA)
This is the only register that supports Byte access and 16-bit Word access. The upper address bit of the PCI Configuration
Space is specified by the G2P Configuration Address Register (G2PCFGADRS). The lower two bits of the address are
specified by the lower two bits of the offset address in this register as shown in Table 16-62.
Rev. 3.1 November 1, 2005
Default
Default
NAME
NAME
Bits
31:0
TYPE
TYPE
Mnemonic
ICD
Access Size
32-bit
16-bit
8-bit
31
15
30
14
Field Name
Initiator
Configuration
Data
29
13
Table 16-62 PCI Configuration Space Access Address
Configuration Space
Address [1:0]
00
00
10
00
01
10
11
28
12
Figure 16-61 G2P Configuration Data Register
Table 16-63 G2P Configuration Data Register
27
11
Description
Initiator Configuration Data Register (Default--)
This is a data port that is used when performing initiator PCI configuration
access. PCI configuration Read or Write transactions are issued when this
register is read to or written from.
26
10
25
9
16-71
Offset Address
Little Endian Mode
0xD1A4
0xD1A4
0xD1A6
0xD1A4
0xD1A5
0xD1A6
0xD1A7
24
8
R/W
R/W
ICD
ICD
23
7
22
6
21
5
Big Endian Mode
0xD1A4
0xD1A6
0xD1A4
0xD1A7
0xD1A6
0xD1A5
0xD1A4
20
Toshiba RISC Processor
4
19
3
18
2
17
1
R/W
R/W
TX4939
16
0
16
16

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