TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 445

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.4.62. PDMAC Status Register (PDMSTATUS)
Rev. 3.1 November 1, 2005
Bit
63:30
29:24
23:20
19:18
17:16
15:12
11
10
9
8
7
Default
Default
Default
Default
NAME
NAME
NAME
NAME
TYPE
TYPE
TYPE
TYPE
Mnemonic
REQCNT
FIFOCNT
FIFOWP
FIFORP
ERRINT
DONEINT
CHNEN
XFRACT
ACCMP
RESERVED
63
47
31
15
RESERVED
62
46
30
14
Field Name
Rsvd
Request Delay
Time Counter
FIFO Hold Count
FIFO Write
Pointer
FIFO Read
Pointer
Rsvd
Error Interrupt
Status
Normal Transfer
Complete
Interrupt Status
Chain Enable
Transfer Active
Abnormal Chain
Completion
61
45
29
13
60
44
28
12
ERRINT DONEINT CHNEN XFRACT ACCMP NCCMP NTCMP
0x0
59
43
27
11
REQCNT
R
Description
Request Delay Counter (Default: 0x00)
This field indicates the request delay time counter value as 16 × n when the
6-bit value of this field is n.
FIFO Valid Entry Count (Default: 0x0)
This field indicates the number of bytes that was written in the FIFO but not
yet read. This is a diagnostic function.
FIFO Write Pointer (Default: 0x0)
This field indicates the next Write position in the FIFO. This is a diagnostic
function.
FIFO Read Pointer (Default: 0x0)
This field indicates the next Read position in the FIFO. This is a dianostic
function.
Error Interrupt Status (Default: 0x0)
Indicates whether to signal an error interrupt.
1: An error interrupt request exists.
0: No error interrupt request exists.
Normal Transfer Complete Interrupt Status (Default: 0x0)
Indicates whether a Normal Transfer Complete Interrupt is signaled.
This bit becomes “1” when either the Normal Chain Complete bit (NCCMP) is
set and the Normal Chain Complete Interrupt Enable bit (NCCMPIE) is set, or
when the Normal Data Transfer Complete bit (NTCMP) is set and the Normal
Data Transfer Complete Interrupt Enable bit (NTCMPIE) is set.
1: A Normal Transfer Complete Interrupt request exists.
0: No Normal Transfer Complete Interrupt request exists.
Chain Enable (Default: 0x0)
This bit is a copy of the Chain Enable bit in the PDMAC Control Register.
Transfer Active (Default: 0x0)
This bit is a copy of the Transfer Active bit in the PDMAC Control Register.
Abnormal Chain Complete (Default: 0x0)
1: Indicates that the Chain transfer ended in an error state. In other words,
this reflects an OR operation of the PDMAC Status Register bits [3:0].
0: Indicates that no error has occurred in the Chain transfer since the previous
error bit was cleared.
Note:
clear this bit.
Table 16-75 Status Register
R
Figure 16-73 Status Register
0x0
58
42
26
10
R
Bits [3:0] of the PDMAC Status Register must be cleared in order to
0x0
57
41
25
R
9
16-81
RESERVED
RESERVED
0x0
56
40
24
R
8
0x0
55
39
23
R
7
R/W1C R/W1C
0x0
54
38
22
FIFOCNT
6
R
0x0
53
37
21
5
Rsvd CFGERR PCIERR CHNERR DATAERR
52
36
20
Toshiba RISC Processor
4
R/W1C R/W1C R/W1C R/W1C
0x0
51
35
19
3
FIFOWP
R
0x0
50
34
18
2
0x0
49
33
17
1
FIFORP
R/W
⎯
R
R
R
R
⎯
R
R
R
R
R
TX4939
R
0x0
48
32
16
0
16
16