TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 448

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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PCIC
16.5. PCI Configuration Space Register
16.5.1. Configuration Space Register Map
The PCI Configuration Space Register is accessed using PCI Configuration cycles by way of an external PCI host device
only when in the Satellite mode. Table 16-76 lists registers contained within the PCI Configuration Space Register. The
registers in the table with a shaded background are those whose values can be rewritten using EEPROM.
Registers at addresses 0x00 through 0x41 can use the corresponding PCI Controller Control Register to access from the
TX49/H4 core when in the Host mode. Please refer to the explanation of the corresponding PCI Controller Control registers
for more information about these registers. This section only describes the registers that are accessed from the PCI
Configuration Space.
Also, it is possible to read some of the fields in the Status Register and PMCSR register from the Satellite Mode PCI Status
Register.
Please refer to the PCI Bus Specifications for more information on the PCI Configuration Register.
Rev. 3.1 November 1, 2005
Address
44h-DBh
E4h-FFh
Offset
DCh
0Ch
1Ch
2Ch
3Ch
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h
40h
E0h
31
Power Management Capabilities (PMC)
Reserved
Max_Lat
BIST
Subsystem ID
Device ID
Reserved
24
Status
Table 16-76 PCI Configuration Space Register
23
Memory Space 0 Lower Base Address
Memory Space 0 Upper Base Address
Memory Space 1 Lower Base Address
Memory Space 1 Upper Base Address
Header Type
Class Code
PCI Register WORD (32-bit)
Memory Space 2 Base Address
Reserved
Reserved
Min_Gnt
I/O Space Base Address
Reserved
Reserved
Reserved
Reserved
Reserved
16
16-84
Retry Timeout Value
15
(Next_Item_Ptr)
Latency Timer
Next Item Ptr
Power Management Control/Status
Interrupt Pin
Subsystem Vendor ID
Register (PMCSR)
Command
Vendor ID
8
Capabilities Pointer
7
Cache Line Size
TRDY Timeout
Interrupt Line
Capability ID
Revision ID
(Cap_Ptr)
(Cap_ID)
Value
Toshiba RISC Processor
0
PCIID
PCISTATUS
PCICCREV
PCICFG1
P2GM0PLBASE
P2GM0PUBASE
P2GM1PLBASE
P2GM1PUBASE
P2GM2PBASE
P2GIOPBASE
PCISID
PCICAPPTR
PCICFG2
G2PTOCNT
Corresponding
Register
TX4939
16
16

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