TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 451

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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PCIC
16.5.6. Power Management Capability Register (PMC)
Rev. 3.1 November 1, 2005
Bit
15:11
10
9
8:6
5
4
3
2:0
Default
NAME
TYPE
Mnemonic
PMESPT
D2SPT
D1SPT
DSI
PMECLK
PMVER
15
14
PMESPT
Field Name
PME Output
Support
D2 Support
D1 Support
Reserved
DSI
Reserved
PME Clock
Power
Management I/F
Version
0x19
13
R
12
11
Description
PME_ Support (Fixed Value: 0x09)
Indicates that the PME* signal can be output from the state where the bit is
set to “1”.
Bit 15: Can output the PME* signal from the D3cold state.
Bit 14: Can output the PME* signal from the D3hot state.
Bit 13: Can output the PME* signal from the D2 state.
Bit 12: Can output the PME* signal from the D1 state.
Bit 11: Can output the PME* signal from the D0 state.
Note:
signal from the D0 and the D3hot states.
D2_Support (Fixed Value: 0)
0: Indicates that the D2 state is not supported.
D1_Support (Fixed Value: 0)
0: Indicates that the D1 state is not supported.
DSI (Fixed Value: 0)
0: Indicates that Device Specific Initialization is not required.
PME Clock (Fixed Value: 0)
0: Indicates that the PCI Clock is not required to assert the PME* signal.
Version (Fixed Value: 0x2)
2: Indicates compliance with "PCI Power Management Interface
Specification" Version 1.1.
D2SPT D1SPT
Figure 16-79 PMC Register
Table 16-82 PMC Register
10
R
0
With the TX4939 PCI Controller, it is possible to output the PME*
R
9
0
16-87
8
Reserved
7
6
DSI
R
5
0
Reserved PMECLK
Toshiba RISC Processor
4
0xDE
R
0
3
2
PMVER
0x2
R
1
R/W
R
R
R
R
R
R
TX4939
0
16
16

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