TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 459

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ATA100
17.3.2. Registers in slave mapping
17.3.2.1. DMA Command Register (800h)
17.3.2.2. DMA Status Register (802h)
Rev. 3.1 November 1, 2005
Bits
D7:D5
D4
D3
D2:D1
D0
Bits
D7
D6
D5
D4:D3
D2
D1
D0
Default
Default
Name:
Name:
R/W:
R/W:
Bit:
Bit:
D15
D15
Mnemonic
PRD_NOT_E
N
R_OR_WCTR R_OR_WCTR
START_STO
PBM
Mnemonic
DR1_DMACP DR1_DMACP
DR0_DMACP DR0_DMACP
INT_IDE
ERROR
BM_ACT
D14
D14
D13
D13
Field Name
Reserved
PRD_NOT_EN
Reserved
START_STOPBM Data transfer starts by setting this bit to 1. Data to be transferred is specified in both
Field Name
Reserved
Reserved
INT_IDE
ERROR
BM_ACT
D12
D12
000000000
00000000
Reserved
RO
RO
Reserved
D11
D11
Description
PRD not enable, if this is ‘1’ the DMA will use the Transfer Start Address for Source or
Destination address as described in ATA100 Core
This bit specifies a direction of data transfer
0 : Host
1 : Device
This bit is mapped to Direction bit in ATA100 Core
Transfer Word Counter register and Sector Counter register. This bit will be cleared
when transfer terminates. And following is the clear condition for this bit.
a)
b)
c)
Data Transfer termination except above condition does not clear this bit.
This bit is mapped to Start bit in ATA100 Core
Description
Reserved
Fixed to “0”.
DR1_DMACP [Drive1 (Slave) DMA Capable]
Is set to “1” when a slave drive can perform DMA.
DR0_DMACP [Drive0 (Master) DMA Capable]
Is set to “1” when the master drive can perform DMA.
INT_IDE (RWC) [Interrupt]
Is “1” when data transfer completes. This bit is cleared by writing “1” to it.
When this bit is set to ‘1’, the following bits of the ATA Interrupt Controller Register will be
reset: bits [15:8] (Mask Address Error INT, Mask Reach Multiple INT, Mask DEV
Timing Error, Mask Ultra DMA DEV Terminate, Mask Timer INT, Mask Bus Error, Mask
Data Transfer End, Mask Host INT), and bits [1:0] (Data Transfer End, Host INT).
ERROR (RWC)
Is set to “1” when an error occurs during data transfer to or from the system memory.
This bit is cleared by writing a “1” to it. Refer to the status register in the configuration
space for details about the error.
BM_ACT(RO) [Bus Master IDE Active]
Is set to “1” when the command register start bit is set to “1.” This bit is set to “0” either
when the start bit is set to “0” (aborted) or when the last transfer in the current cycle is
executed and the area descriptor EOT is set (terminated normally).
Figure 17-2 Command Register
D10
D10
Figure 17-3 Status Register
Power On Reset
Soft Reset (bit[15] of System Control Register)
Termination of specified Data transfer including command packet
D9
D9
Device
Host
17-5
D8
D8
D7
D7
Reserved
DR1_D
MACP
000
RW
RO
D6
D6
0
DR0_D
MACP
RW
D5
D5
0
PRD_
NOT_
R/W
D4
EN
D4
Reserved
0
Toshiba RISC Processor
RO
0
_WCT
R_OR
RW
D3
D3
R
0
RWC
INT_
IDE
D2
D2
Reserved
0
RO
00
ERRO
RWC
D1
D1
R
0
TX4939
START
_STOP
BM_
ACT
RW
BM
RO
D0
D0
0
0
17
17