TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 461

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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ATA100
17.3.2.3.1. PRD
The PRD (Physical Region Descriptor) is a table that is used to define the physical memory area used in bus master
transfers. It is provided for handling situations where the memory area can only be used in small divided sections when
performing bus master transfer. The minimum configuration unit of a PRD is two double-words, with each PRD located at
contiguous addresses so that they can be read by the hardware. The software prepares PRDs in a memory area.
17.3.2.3.2. PRD Table
The PRD table has its PRD data arranged in contiguous locations beginning with the address specified by the base address.
One PRD consists of two double-words (64 bits). The base address is specified by an I/O register.
17.3.2.3.3. PRD Configuration
Rev. 3.1 November 1, 2005
Bits
D63
D62:D48
D47:D35
D31:D3
Default
Default
Default
Default
Name:
Name:
Name:
Name:
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
*1 : Byte Count[0]
*2 : Memory Region Physical Base Address[0]
Bit:
Bit:
EOT
D31
D15
D63
D47
RW
0
Mnemonic
EOT
Byte Count
Memory
Region
Physical Base
Address
D30
D14
D62
D46
Offset
0x00
0x08
0x10
0x18
D29
D13
D61
D45
Field Name
EOT
Reserved
Byte Count
Memory Region
Physical Base
Address
D28
D12
D60
D44
Memory Region Physical Base Address [15:3]
PRD
PRD
PRD
PRD (Last data)
D27
D11
D59
D43
Description
EOT
This bit designates the end of the table. Set this bit to “1” for the last entry of the table.
The DMA controller checks this bit and terminates DMA processing when it is “1.”
Byte Count [15:3]
These bits specify the size of the memory area. The 3 least significant bits of this byte
count must be “0” since the address needs to be double word-aligned (8 bytes)
Memory Region Physical Base Address [31:3]
These bits specify the start address of the memory area in which to store data during
DMA transfer. The 3 least significant bits of this address must be “0” since the address
needs to be double word-aligned (8-bytes).
Memory Region Physical Base Address [31:16]
Figure 17-5 PRD Configuration
D26
D10
D58
D42
Byte Count [15:3]
D25
D57
D41
RW
RW
D9
*?*
0
17-7
D24
D56
D40
D8
RW
Reserved
0
D23
D55
D39
RO
D7
0
D22
D54
D38
D6
D21
D53
D37
D5
D20
D52
D36
D4
Toshiba RISC Processor
D19
D51
D35
D3
D18
D50
D34
D2
*?*
*2
*1
0
0
D17
D49
D33
*?*
D1
*2
*1
0
0
TX4939
D48
D32
D16
D0
*?*
*2
*1
0
0
17
17

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