TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 462

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ATA100
17.3.2.4. System Control Register (C00h)
This register is the same as System Control register in ATA100 CORE. The register is shared with both Master device and
Slave device.
Rev. 3.1 November 1, 2005
BIT
Bit[15]:
Bit[14]:
Bit[13]:
Bit[12]:
Bit[11]:
Bit[10:8]
Soft Reset
Bit 15
Bit 7
R/W
W
0
0
NAME
Soft Reset
FIFO Reset
PDIAGN
DASPN
ATA Hard Reset
Command Transfer
Mode Select [2:0]
FIFO Reset
Data Transfer Mode Select
Bit 14
Bit 6
R/W
W
0
0
PDIAGN
Bit 13
Bit 5
R/W
R
1
0
Description
This bit resets the controller.
This bit resets the FIFO control block. You do not have to set this bit during normal
operation. (This bit is only used during the controller test.)
Note:
execute register read operation until 7-12 GBUSCLK cycles pass.
You can use this bit to monitor the PDIAGN signal on the ATA Bus.
You can use this bit to monitor the DASPN signal on the ATA Bus.
automatically cleared when the time set by the Host Reset Timer Register elapses.
However, you must take note that after this bit is set, the device will ignore any
commands that are set until this bit is cleared.
You can use this field to select the transfer mode that you will use when accessing ATA
Registers such as command registers on the target device. Access to the Data Register
from TX4939 follows the Data transfer timing.
000:
001:
010:
011:
100:
101, 110, 111: Reserved
The minimum cycle times mentioned above are specific values
Example: The following transfer modes are selected when using Command Transfer
Mode Select to select PIO Mode 3 and Data Transfer Mode Select to select Ultra DMA
Mode 1.
1. ATA registers except the Data Register → PIO Mode 3
2. Data Register → PIO Mode 3
3. Data Transfer → Ultra DMA Mode 1
You can activate a Reset signal that is sent to the ATA Bus by setting this bit. This bit is
Figure 17-6 System Control Register
Table 17-1 System Control Register
(Timing is the same as when using Data Transfer Mode Select to select PIO Mode 3.)
When you set this bit, after the G-Bus BSTARTN signal is asserted, do not
Selects PIO Mode 0 (Minimum Cycle Time: 600 ns)
Selects PIO Mode 1 (Minimum Cycle Time: 383 ns)
Selects PIO Mode 2 (Minimum Cycle Time: 330 ns)
Selects PIO Mode 3 (Minimum Cycle Time: 180 ns)
Selects PIO Mode 4 (Minimum Cycle Time: 120 ns)
DASPN
Bit 12
Bit 4
R/W
R
1
0
17-8
Break Enable
ATA Hard
Bit 11
Reset
Bit 3
R/W
R/W
0
0
End Break
Bit 10
Bit 2
R/W
R/W
0
0
Command Transfer Mode Select
Toshiba RISC Processor
Auto DMA
Enable
Bit 9
Bit 1
R/W
R/W
0
0
Access Now
Bit 8
Bit 0
R/W
R
0
0
TX4939
17
17