TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 467

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ATA100
17.3.3.4. Additional Control Register (C28h)
Rev. 3.1 November 1, 2005
BIT
Bit[13:12]:
Bit[11:10]:
Bit[9]:
Bit[8]:
Bit[7]:
Bit[6]:
Bit[5]:
Bit[4];
Bit[3:2]:
Note 1:
Reserved
Bit 15
Bit 7
R
1
0
-
Not Used
Byte Swap Bit[4] and Endian Control Bit[3:2] can control Endianness of ATA100 Interface.
NAME
Not Used
Bus Mode
All Pause
All Idle
-
Transfer Pause
Not Used
Byte Swap
Note 1
Endian Control
Note 1
Transfer
CPU Endianness
Bit 14
Pause
Bit 6
R/W
R
1
0
Little Endian
Big Endian
Not Used
Bit 13
Bit 5
R/W
0
0
-
Figure 17-9 Additional Control Register
Table 17-2 Additional Control Register
Description
User should write only 00 to this field. Other values will be undefined
This field determines the bus width when transferring data as the Bus Master.
11: Reserved
10: 64-bit bus. Only support 64-bit bus.
Note: Data transfer rate on the ATA Bus is influenced by these bits.
You can use this bit to acknowledge that the receiving of data from the device has been
paused. Also, this bit is only set when bit [6](Transfer Pause ) is set.
1: Transfer had been paused.
0: Normal state
You can use this bit to acknowledge that the sending/receiving of data to/from the
device has been stopped. Setting bit [6](Transfer Pause) does not set this bit.
1: Transfer has stopped
0: Normal state
Reserved
You can pause transfer from the device by setting this bit.
1: Pause transfer
0: Normal state
Reserved
1: Swap all the bytes on 64 bit GBUS DATA
0: No Swap.
Default is the System GBUS Endian control bit
Note: This bit is applied on GBUS DATA in/out to ATA control for data transfer only by
ATA DMA
This field determines the Endian for when transferring data as the Bus Master. The
following example shows a 64-bit bus with a correlation between the ATA Bus data and
G-Bus data of aabb_ccdd_eeff_ggiih:
11: 1st Data ccddh 2nd Data aabbh 3rd Data ggiih 4th Data eeffh
10: 1st Data aabbh 2nd Data ccddh 3rd Data eeffh 4th Data ggiih
01: 1st Data eeffh 2nd Data ggiih 3rd Data aabbh 4th Data ccddh
00: 1st Data ggiih 2nd Data eeffh 3rd Data ccddh 4th Data aabbh
Not Used
Recommended Value for Bit[4:2]
Byte Swap
GENDIAN
Bit[4] = 0, Bit[3] = 0, Bit[2] = 0
Bit[4] = 1, Bit[3] = 0, Bit[2] = 0
Bit[4] = 1, Bit[3] = 0, Bit[2] = 0
Bit[4] = 0, Bit[3] = 1, Bit[2] = 0
Bit 12
Bit 4
R/W
R/W
0
17-13
Bit 11
Bit 3
R/W
R
1
0
Endian Control
Bus Mode
Bit 10
Bit 2
R/W
R
0
0
Endianness of ATA100
Toshiba RISC Processor
All Pause
Little Endian
Little Endian
Big Endian
Big Endian
Bit 9
Bit 1
R
R
0
0
Not Used
All Idle
Bit 8
Bit 0
R
R
1
1
TX4939
17
17