TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 474

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ATA100
Rev. 3.1 November 1, 2005
Detection Item
t
t
t
t
t
t
BIT
Bit[5]:
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1]:
Bit[0]:
B
FS
LI
RFS
RP
SS
(PIO Mode)
(UDMA Mode)
(UDMA Mode)
(UDMA Mode)
(UDMA Mode)
(UDMA Mode)
Note:
When the INT_IDE of DMA Status Register is set to “1”, the following bits of Interrupt Control
Register will be reset: bits [15:8] (Mask Address Error INT, Mask Reach Multiple INT, Mask DEV
Timing Error, Mask Ultra DMA DEV Terminate, Mask Timer INT, Mask Bus Error, Mask Data
Transfer End, Mask Host INT), and bits [1:0] (Data Transfer End, Host INT).
NAME
DEV Timing Error
Ultra DMA DEV
Terminate
Timer INT
Bus Error
Data Transfer End
Host INT
Spec. Value
Error Detection Value
Mode
Spec. Value (MAX)
Error Detection Value
Mode
Spec. Value (MAX)
Error Detection Value
Mode
Spec. Value (MAX)
Error Detection Value
Mode
Spec. Value (Min)
Error Detection Value
Mode
Spec. Value (Min)
Error Detection Value
Description
Interrupt status that indicates timing of a control signal from the device is out of spec.
when performing data transfer with the device. Setting “1” to this bit clears this interrupt
status. The specifications for confirming timing are as follows:
1. PIO Mode
2. Ultra DMA Mode tFS (First Strobe Time)
tSS (Time from STROBE edge to negation of DMARQ or assertion of STOP)
The Table 17-5 shows the threshold values for detecting timing errors. However, error
detection is not performed in the case of tRFS since the time period from when
HDMARDY is negated to when STOP is asserted is shorter than the error detection
threshold when in Host terminating an Ultra DMA data-in burst Mode0-3.
Interrupt status that indicates the device terminated Ultra DMA transfer. Setting “1” to
this bit clears this interrupt status.
Interrupt status that indicates the Host Reset timer reached the defined time. Setting “1”
to this bit clears this interrupt status.
Interrupt status that indicates the Bus error occurred when this controller becomes the
Bus Master and executes data transfer. Setting “1” to this bit clears this interrupt status.
Before clearing this bit, set “1” to bit [14](FIFO Reset) of System Control Register and
reset FIFO. The Start bit (bit[0]) in DMA Command register is not cleared when the bus
error occurred, so you may set “1” to bit [15] (Soft Reset) of System Control1 register to
reset this Controller.
Interrupt status that indicates data transfer ended. This bit is also set when the transfer
of command packets ends. Setting “1” to this bit clears this interrupt status.
This bit indicates that INTRQ, which is the interrupt signal from the device, is active.
Setting “1” to this bit clears this interrupt status.
Table 17-4 Interrupt Control Register
Table 17-5 Timing Error Threshold
tLI (Limited Interlock Time)
tRFS (Ready to Final Strobe Time)
tRP (Minimum Time to assert STOP or negate DMARQ)
1250(Max)
>1270
Mode0
230
270
Mode0
150
180
Mode0
75
260
Mode0
160
140
Mode0
50
30
17-20
tB (IORDY Pulse Width)
(in nsec)
Mode1
200
240
Mode1
150
180
Mode1
70
180
Mode1
125
100
Mode1
50
30
Mode2
170
210
Mode2
150
180
Mode2
60
140
Mode2
100
80
Mode2
50
30
Mode3
130
170
Mode3
100
130
Mode3
60
160
Mode3
100
80
Mode3
50
30
Toshiba RISC Processor
Mode4
120
160
Mode4
100
130
Mode4
60
110
Mode4
100
80
Mode4
50
30
Mode5
90
130
Mode5
75
110
Mode5
50
80
Mode5
85
60
Mode5
50
30
TX4939
17
17