TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 475

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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ATA100
17.3.3.19. ATAPI Packet Command Register (CB8h)
17.3.3.20. Bus Transfer Count High Register (CC0h)
You can know the transfer count when transferring data on the G-Bus when this ATA controller is the Bus Master. The total
transfer count is set in this controller. When transfer starts, the total number of transfers to be performed is set in this register
and this number is decremented when each transfer is performed.
Rev. 3.1 November 1, 2005
BIT
Bit[15:0]:
Bit 15
Bit 15
Bit 7
Bit 7
W
W
R
0
0
0
0
-
NAME
Packet
Bit 14
Bit 14
Bit 6
Bit 6
W
W
R
0
0
0
0
-
Not Used
Figure 17-25 Bus Transfer Count High Register
Figure 17-24 ATAPI Packet Command Register
Bit 13
Bit 13
Bit 5
Bit 5
Table 17-6 ATAPI Packet Command Register
W
W
R
0
0
0
0
-
Description
Use this register to issue the ATAPI command packet to the device.
This Register consists of a 16-stage FIFO. You can transfer a command packet to the
device by setting the prescribed command packet in FIFO, setting the transfer count in
bits [11:8](Packet Transfer Count) of the Packet Transfer Control Register, then setting
bit [0](Packet Start) of the Packet Transfer Control Register to “1”.
Bus Master Transfer Count[23:16]
Bit 12
Bit 12
Bit 4
Bit 4
W
W
R
0
0
0
0
-
Packet[15:8]
17-21
Packet[7:0]
Bit 11
Bit 11
Bit 3
Bit 3
W
W
R
0
0
0
0
-
Bit 10
Bit 10
Bit 2
Bit 2
W
W
Bus Master Transfer Count[26:24]
R
R
0
0
0
0
Toshiba RISC Processor
Bit 9
Bit 1
Bit 9
Bit 1
W
W
R
R
0
0
0
0
Bit 8
Bit 0
Bit 8
Bit 0
W
W
R
R
0
0
0
0
TX4939
17
17

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