TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 477

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ATA100
17.3.3.23. Packet Transfer Control Register (CD8h)
This register makes Packet transfer related settings.
17.3.3.24. Transfer Start Top Address Register (CE0h)
This register sets the read/write start top start address of the transfer that this controller outputs to the G-Bus.
Rev. 3.1 November 1, 2005
BIT
Bit[12]:
Bit[11:8]:
Bit[0]:
Bit 15
Bit 15
Bit 7
Bit 7
0
0
0
0
-
-
-
-
NAME
Packet Transfer Mode You can use this bit to set the transfer mode of the command packet.
Packet Transfer Count You can use this bit to set the command packet transfer count. Set the value that is
Packet Start
Not Used
Bit 14
Bit 14
Bit 6
Bit 6
0
0
0
0
-
-
-
-
Not Used
Bit 13
Figure 17-28 Packet Transfer Control Register
Bit 13
Bit 5
Bit 5
Table 17-8 Packet Transfer Control Register
0
0
0
0
-
-
-
-
Description
1: Data transfer timing
of the System Control Register.)
0: PIO data transfer timing
(Packet data is transferred in PIO mode when the data transfer mode is set to Multiword
DMA or Ultra DMA. The same transfer mode selected by bits [10:8] (Command Transfer
Mode Select) of the System Control Register is used.)
equal to the transfer count – 1.
You can use this bit to initiate transfer of the command packet.
(Execute transfer using the transfer mode set by bits [7:4] (Data Transfer Mode Select)
Not Used
Transfer
Bit 12
Packet
Bit 12
Mode
Bit 4
Bit 4
R/W
0
0
0
0
-
-
-
17-23
Not Used
Bit 11
Bit 11
Bit 3
Bit 3
R/W
R/W
0
0
0
0
-
-
Transfer Start Address [35:32]
Bit 10
Bit 10
Packet Transfer Count
Bit 2
Bit 2
R/W
R/W
0
0
0
0
-
-
Toshiba RISC Processor
Bit 9
Bit 1
Bit 9
Bit 1
R/W
R/W
0
0
0
0
-
-
Packet
Start
Bit 8
Bit 0
Bit 8
Bit 0
R/W
R/W
R/W
0
0
0
0
-
TX4939
17
17