TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 478

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ATA100
17.4. Actual Operation Timing
17.4.1. Data transfer in the PIO mode
The above figures are timing diagrams of read/write transfer by PIO Mode 4. Following are the steps for setting up the
software used when transferring data.
Rev. 3.1 November 1, 2005
(1)
(2)
(3)
(4)
(5)
ATA_CLK
HA
CS1N
CS0N
ATA_CLK
HA
CS1N
CS0N
ATD_IN
DIORN
ATD_OUT
DIOWN
ATDBUS_E
Data transfer in the PIO Mode (Read)
Data Transfer in the PIO Mode (Write)
Use bits [7:4] of the System Control Register to select the PIO mode.
Use the Transfer Word Count Register to set the word count of data to be transferred with a
device.
Use the Transfer Sector Count Register to set the sector count of data to be transferred with a
device.
This controller becomes the Bus Master then the 36-bit start address at which data transfer starts
is set in the Transfer Start Lower Register, Transfer Start Upper Register, and the Transfer Start
Top Register. Then, the maximum number of words that this controller transfers as the Bus Master
using a single Burst transfer is set in the Burst Count Upper Register and Burst Count Lower
Register..
Use bit [3] (R_ORWCTR) of the DMA Command Register to determine the data transfer direction.
17-24
Toshiba RISC Processor
TX4939
17
17