TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 480

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ATA100
The following table shows the PIO transfer timing in each mode.
Rev. 3.1 November 1, 2005
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Note 1)
Note 2)
Note 1)
Note 2)
Mode0
Mode1
Mode2
Mode3
Mode4
Mode
Read the Status Register of the ATA Shadow Register, and confirm that the BSY bit is “0”.
Read the Status Register of the ATA Shadow Register, and confirm that the DRQ bit is “0”. An
error has occurred if the DRQ bit is “1”.
Set the DEV bit of the Device/Head Register of the ATA Shadow Register.
Confirm that the BSY bit of the Status Register of the ATA Shadow Register is “0”.
Confirm that the DRQ bit of the Status Register of the ATA Shadow Register is “0”. An error has
occurred if the DRQ bit is “1”.
Read the LBA Mid Register and LBA High Register of the ATA Shadow Register, and confirm
Signature.
Execute the IDENTIFY DEVICE command and fetch the device information.
The specification requires the device recognition sequence to be performed each time you set
up the software used for transferring data.
The specification specifies that the BSY and DRQ bits confirmed from the Status Register of the
ATA Shadow Register are confirmed in the following order: clear BSY → set DRQ.
HA, CS0N, CS1N: Are automatically set as follows at the point when PIO transfer starts: HA=0h,
CS0N=0, CS1N=1.
ATD_IN[15:0]:
During read →
ATD_OUT[15:0]:
During write→
(100MHz) cycles after the DIOWN rise.
130 nsec
100 nsec
50 nsec
50 nsec
40 nsec
DIORN/DIOWN
HA, CS Valid -
Enable
Send to the FIFO in the controller at the DIORN rise.
Define data simultaneous to the DIOWN fall. Hold the value for 2 ATA_CLK
Table 17-9 PIO Transfer Timing
180 nsec
150 nsec
120 nsec
100 nsec
90 nsec
DIORN/DIOWN
Width
17-26
380 nsec
210 nsec
110 nsec
70 nsec
20 nsec
DIORN/DIOWN
HA, CS Invalid
Disable -
Toshiba RISC Processor
600 nsec
390 nsec
240 nsec
180 nsec
120 nsec
Cycle Time
TX4939
17
17