TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 482

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ATA100
The following table shows the transfer timing when using Multiword DMA.
Rev. 3.1 November 1, 2005
Mode0
Mode1
Mode2
Mode
Note 1)
Note 2)
90 nsec
60 nsec
40 nsec
DIORN/DIOWN Enable
HA, CS0N, CS1N: Are automatically set as follows at the point when Multiword DMA
transfer starts: HA=0h, CS0N=1, CS1N=1.
ATD_IN[15:0]:
During read →
ATD_OUT[15:0]:
During write→
ATA_CLK (100MHz) cycles after the DIOWN rise.
HA, CS Valid -
Table 17-10 Multiword DMA Transfer Timing
Send to the FIFO in ATA100 core at the DIORN rise.
Define data simultaneous to the DIOWN fall. Hold the value for 3
DIORN/DIOWN Width
260 nsec
100 nsec
90 nsec
17-28
210 nsec
80 nsec
70 nsec
DIORN/DIOWN
HA, CS Invalid
Disable -
Toshiba RISC Processor
480 nsec
160 nsec
120 nsec
Cycle Time
TX4939
17
17