TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 496

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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EMAC
18.3. Detailed explanation
The two Ethernet Controllers in TX4939 are identical to each other both in behavior and application and differ only in the
method used to access each of the two Ethernet Controllers register space and their respective interrupt mapping. This
difference is due to the fact that each of the two Ethernet Controllers are instantiated as a unique PCI device on the
internal PCI Bus thereby requiring unique IDSEL and Interrupt signals for each of the two Ethernet Controllers. The
following is a detailed explanation of one TX4939 Ethernet Controller. The description provided in the following sections
is applicable to all two Ethernet Controllers unless specified otherwise.
18.3.1. Accessing the Ethernet Controller
Both Ethernet Controllers are connected to the chip-internal PCI Bus. The chip-internal PCI Bus is connected to the G-
Bus via the PCI Controller (PCIC1). Therefore, you should access the two Ethernet Controllers via PCI Controller No. 2.
PCI Controller No. 2 is a circuit that is equivalent to the PCI Controller No. 1(PCIC). The Ethernet Controllers only
supports the PCI Controller No. 2 functions that it requires to operate. Following are the differences with PCIC.
Rev. 3.1 November 1, 2005
Host mode only. (Does not support the Satellite mode.)
Does not support EEPROM for Configuration data storage
Does not support an external PCI arbiter
Does not support type 1 configuration
Does not support the Interrupt Acknowledge command
Does not support the Special Cycle command
18-4
Toshiba RISC Processor
TX4939
18
18

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