TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 499

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.3.1.2. Interrupt signaling
PCI Controller No. 2 signals the following interrupt to the Interrupt Controller (IRC):
This interrupt is similar to a combination of two PCI Controller 0 interrupt signals into a single interrupt signal. For the
content of each interrupt, see subsection 10.3.11.
The two Ethernet Controllers signals the following interrupts to the Interrupt Controller (IRC):
For the content of these interrupts, see 18.4.3.9 Interrupt Source Register.
18.3.1.3. IDSEL signal connections
Internal PCI Bus AD (Address, Data) signals are connected to Ethernet Controller IDSEL signals. The connection
destination follows below.
18.3.2. Data structure
The Ethernet Controller exchanges control information and data using the following data structure.
Figure 18-3 shows the relationships of the above data structures.
A frame descriptor consists of a 4-byte pointer that points to the next frame, a field dedicated to a system or application
program, a frame status field, a control field for all frames, and a corresponding group buffer descriptor. The buffer
descriptor contains a pointer to the data buffer and buffer control information. The data buffer is a data storage area in
Byte units that is stored in either the Little Endian or Big Endian order. For details on these data structures, see 18.3.7
Memory configuration.
The DMA engine responds to the transfer of data that is positioned at the byte boundaries. Frame descriptors must be
aligned to 16-Byte boundaries. Also, buffer descriptors must be aligned to 8-Byte boundaries. The DMA engine Burst
transfers 4-Byte aligned data as much as possible. However, whether data buffers are aligned to 4-Byte boundaries or
not does not have much effect on performance. The DMA engine accesses only words or parts of words not aligned to 4-
Byte boundaries at the start and end of Block transfer. Part way through Block transfer however, the DMA engine
performs word-unit 4-Byte access.
Rev. 3.1 November 1, 2005
Frame Descriptors
Buffer Descriptors
Data Buffer
PCIC1 Interrupt (Interrupt Number: 36, PCIC1INT)
Ethernet Channel 0 Interrupt (Interrupt Number: 6)
Ethernet Channel 1 Interrupt (Interrupt Number: 43)
Ethernet Channel 0 IDSEL signal: Internal PCI Bus AD[31]
Ethernet Channel 1 IDSEL signal: Internal PCI Bus AD[30]
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Toshiba RISC Processor
TX4939
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