TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 5

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Index
List of Contents
LIST OF CONTENTS .......................................................................................................................................................... I
LIST OF FIGURES ........................................................................................................................................................... XII
LIST OF TABLES ............................................................................................................................................................XIX
CHAPTER 1. FEATURES................................................................................................................................................ 1-1
CHAPTER 2. INTERNAL BLOCK DIAGRAM................................................................................................................. 2-1
CHAPTER 3. PIN ASSIGNMENT AND FUNCTION ........................................................................................................ 3-1
CHAPTER 4. BOOT CONFIGURATION ......................................................................................................................... 4-1
CHAPTER 5. CLOCK GENERATORS ............................................................................................................................ 5-1
Rev. 3.1 November 1, 2005
1.1. A
1.2. I
1.3. S
1.4. E
2.1. TX4939 S
2.2. TX49/H4 C
2.3. P
2.4. TX4939 P
3.1. P
3.2. P
3.3. P
3.4. P
4.1. B
4.2. B
1.4.1. Two ATA100 for DVD Recorder...................................................................................................................... 1-3
1.4.2. One ATA100 and Two Ethernet ...................................................................................................................... 1-4
2.3.1. Strategy for Power Management.................................................................................................................... 2-3
2.3.2. Power Management for Internal Controller .................................................................................................... 2-3
2.3.3. Battery Back-Up Real Time Clock.................................................................................................................. 2-3
3.3.1. System Clock and RESET Signals................................................................................................................. 3-5
3.3.2. DDR SDRAM Interface Signals...................................................................................................................... 3-5
3.3.3. VIDEO Port Interface Signal .......................................................................................................................... 3-6
3.3.4. ATA100 Channel 0 Interface .......................................................................................................................... 3-6
3.3.5. ATA100 Channel 1 Interface .......................................................................................................................... 3-6
3.3.6. External Bus Interface Signals ....................................................................................................................... 3-7
3.3.7. ISA Interface Signals...................................................................................................................................... 3-7
3.3.8. Default GPIO.................................................................................................................................................. 3-8
3.3.9. PCI Interface Signals ..................................................................................................................................... 3-8
3.3.10. Ethernet MAC Interface (RMII)..................................................................................................................... 3-9
3.3.11. AC-Link Interface.......................................................................................................................................... 3-9
3.3.12. I2S Interface 2-channel mode ...................................................................................................................... 3-9
3.3.13. I2S Interface 5.1 channel mode ................................................................................................................. 3-10
3.3.14. I2C Interface .............................................................................................................................................. 3-10
3.3.15. SPI Interface .............................................................................................................................................. 3-10
3.3.16. RTC Interface............................................................................................................................................. 3-10
3.3.17. SIO Interface...............................................................................................................................................3-11
3.3.18. Timer Interface ............................................................................................................................................3-11
3.3.19. Interrupt Signals ..........................................................................................................................................3-11
3.3.20. PLL Power and Ground...............................................................................................................................3-11
3.3.21. TEST and EJTAG Debugging Interface...................................................................................................... 3-12
3.4.1. Pin Multiplex for GPIO (Miscellaneous)........................................................................................................ 3-13
3.4.2. Pin Multiplexing for ACLINK and I2S............................................................................................................ 3-13
3.4.3. Pin Multiplex for ATA100-0 (Channel 0) ....................................................................................................... 3-14
3.4.4. Pin Multiplex for ATA100-1 (Channel 1) ....................................................................................................... 3-15
3.4.5. Pin Multiplex for Video port .......................................................................................................................... 3-16
3.4.6. Pin Multiplexing for ISA ................................................................................................................................ 3-17
3.4.7. Pin Multiplexing for PCICLK [4:1] ................................................................................................................. 3-17
MPLEMENTED
BSTRACT
YSTEM
XAMPLE OF
OWER
IN
IN
IN
IN
OOT
OOT
A
A
F
M
SSIGN
LIGNMENT
UNCTION
ULTIPLEXING
C
C
M
ONFIGURATION
ONFIGURATION
B
ANAGEMENT
LOCK
............................................................................................................................................................... 1-1
YSTEM
ERIPHERAL
ORE
T
R
ABLE
F
EFERENCE
......................................................................................................................................................... 3-5
EATURES
(TOP VIEW) ................................................................................................................................... 3-4
D
F
IAGRAM
B
EATURES
.................................................................................................................................................... 3-1
................................................................................................................................................. 3-13
LOCK
F
F
............................................................................................................................................. 4-1
D
UNCTION
EATURE
ETAIL
.......................................................................................................................................... 1-1
D
......................................................................................................................................... 1-2
S
IAGRAM
....................................................................................................................................... 2-2
YSTEM
.................................................................................................................................. 4-2
................................................................................................................................ 2-3
F
............................................................................................................................. 1-3
EATURES
............................................................................................................................ 2-1
............................................................................................................... 2-4
i
Toshiba RISC Processor
TX4939