TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 502

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.3.4. Functional overview
Figure 18-2 is a diagram of the entire Ethernet system. Figure 18-4 and Figure 18-5 are more detailed function block
diagrams of the Ethernet Controller. Figure 18-4 is a function block diagram of DMA. Figure 18-5 is a function block
diagram of MAC.
Figure 18-4 and Figure 18-5 both show the relationship with the DMA-independent interface (DII). DII is an internal
interface that has simple handshake signals and interfaces MAC-internal FIFO with the DMA block-internal DMA buffer.
The two FIFOs in the MAC are 1 Byte wide. The DMA block contains DMA buffers that are wider and deeper than MAC.
Figure 18-4 shows the relationship with the bus-independent interface (BII). The BII is an internal interface that has Bus
Request/Bus Grant protocols for Burst access performed by the Bus Master. The BII makes it possible to connect the
DMA engine to a 32-bit PCI Bus Controller or another bus controller.
Rev. 3.1 November 1, 2005
DMA Reception
PCI Config
Register
Producer
DMA Reception
Consumer
DMA Reception
Buffer
Figure 18-4 DMA Function Block
PCI I/O Control PCI Slave
PCI Master Pipe Register
32
8
Control Status
Register
18-10
PCIC
PCI
DII
BII
Address Data
32
8
DMA Transmission
Buffer
DMA Transmission
Producer
Transmission
Consumer
PCI Bus/DMA
DMA
Buffer Arbiter
Toshiba RISC Processor
G-Bus
TX4939
Rev 2.20
18
18