TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 503

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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EMAC
18.3.4.1. Overview of PCI and DMA
Figure 18-4 shows the PCI Bus configuration, blocks that perform control, DMA buffer and data exchange.
The DMA buffer the DMA engine controls has a transmission area and a reception area. The DMA Transmission buffer
stores the data and status information of multiple packets that are currently being transmitted. The DMA Reception buffer
stores the data and status information of multiple packets that were received. Each buffer has a Producer Block that
controls the data stored in a buffer and a Consumer Block that controls data removed from a buffer.
The PCI Bus/DMA Buffer arbiter determines whether the consumer or producer State Machine has higher priority access
permission to the PCI Bus/DMA Buffer. The priority changes dynamically and, if possible during Burst transfer, gives
priority to the State Machine that controls the PCI Bus. However, when either the MAC Reception FIFO becomes nearly
full or the MAC Transmission FIFO becomes nearly empty during transmission, priority is given to that FIFO. In other
situations, the round-robin scheme is used to provide service in a fair manner.
The DMA Controller block consists of the circuits required for the Bus Master to perform read/write operations via the PCI
Bus.
Rev. 3.1 November 1, 2005
PCI I/O Control Block
Generates and acknowledges PCI control signals.
PCI Slave Control Block
Acknowledges and controls transactions when the Ethernet Controller is the target device.
PCI Master Control Block
Starts and controls transactions requested by the DMA engine of the Ethernet Controller.
PCI Pipe Register Group
Buffers data so the DMA engine can continue Burst transfer with 1-1-1-1 timing over a long period of time.
PCI Configuration Register
Flexibly performs PCI system setup.
DMA Control Status Register
Sets up and controls DMA.
Arbiter Block
Arbitrates access to the PCI Bus or the DMA buffer.
Producer Block, Consumer Block
Controls transmission/reception data output/input to/from the DMA buffer.
Busrt Size Control Circuit
Optimizes PCI and system performance.
Transmission Threshold Control Circuit
Matches transmission latency to PCI Bus latency.
Big Endian Byte Translation Circuit
Supports data transfer to Big Endian format processors.
Buffer Distribution/Sharing Control Circuit
Can distribute then store one frame in multiple buffers. Can also store multiple frames in a single buffer and
increase the usage efficiency.
Polling Control Circuit
Polls transmission packets. Is optional.
Transmission Wakeup Control Circuit
Performs control required to start transmission when the data is prepared.
Early Notification Circuit
Circuit that generates signals for starting to handle reception data before the data ends.
Interrupt Enable Control Circuit
Adjusts controller operation as the protocol requires.
18-11
Toshiba RISC Processor
TX4939
18
18

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