TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 504

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.3.4.2. MAC Overview
Figure 18-5 is a function block diagram of MAC. MAC consists of a Transmission Block, Reception Block, Control/Status
Register group, Flow Control Block, and a Serial Controller. The Serial Controller is an MII station management interface.
The media-independent interface (MII) transfers signals between the 100Base-T compatible physical layer and the
Transmission/Reception Block. MII is described in the IEEE 802.3 standard.
The Transmission Block buffers data transmitted from the MAC Transmission FIFO, assembles packets, and then
transfers them to the MII. Included in the Transmission Block are circuits that generate Preamble Bytes, Jam Bytes, Pad
Bytes, and CRC values. Also included is a parity check circuit, a timer that creates back-off delay when a collision occurs,
and a time that creates a cap between packets that were transmitted.
The Reception Block expands packets received from MII, and then stores them in MAC Reception FIFO. Included in the
Reception Block are a circuit that checks the CRC value, a circuit that generates parity to protect data in the FIFO, and a
circuit that checks the packet length. Also included is an address recognition circuit (ARC) that, based on the receiving
address, judges whether to accept or discard a packet.
You can use a loop back circuit to separate MAC from the MII and physical layer and perform MAC layer testing.
The MAC function block performs control to perform network manipulation such as the following:
Rev. 3.1 November 1, 2005
Control to include a stop request at the end of a packet currently being transmitted or received, and enable or
disable the transmission/reception circuit
Interrupt enable/disable control for each condition
Address recognition control for up to 21 addresses
Counter, status bit for collecting network management data
Loop back or other control that aids network failure diagnosis
Pause operation enable control for pausing the transmitter when a MAC control frame described by Pause
operation is received
MAC control frame transmission control for enabling Pause or other MAC control frame generation even when
the transmitter has paused
MAC control frame pass through control for enabling hardware or software to handle MAC control frames in
another format
MAC Control Status
Register Group
32
MII Station Manager
Reception Block
MDC MDIO
CRC/ARC Filter
ARC
Figure 18-5 MAC Function Block
Generator
Parity
Reception
FIFO
MAC
18-12
RxD[3:0]
8
DII
Control
Flow
MII <-> RMII
Loop Back
Transmission Block
Intergap Timer
Preamble, Jam
Pad, CRC
Generator
Back-off,
Parity Generator
Generator
Toshiba RISC Processor
Transmission
TxD[3:0]
FIFO
MAC
8
Rev 1.00
TX4939
18
18