TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 505

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.3.5. DMA function block
18.3.5.1. DMA Transmission Controller
The DMA Transmission Controller consists of two State Machines: Producer and Consumer. The Producer checks the
frame descriptor of the transmission queue, then controls data transfer from the transmission queue to the DMA
Transmission buffer. Also, after transmission ends, the Producer controls the writing of transmission status information
that expresses the MAC status information for the transmitted data. The Consumer controls transfer of data from the
MAC transmission engine or a large-capacity DMA transmission buffer to a small MAC transmission FIFO.
18.3.5.2. DMA Reception Controller
The DMA Reception Controller consists of two State Machines: Producer and Consumer. Producer controls data transfer
from MAC Reception FIFO to the DMA reception buffer. Consumer allocates buffers from the empty buffer list, writes the
frame descriptor and related buffer descriptor of the packet in the free descriptor area, then controls data transfer via the
PCI Bus from the DMA Reception buffer to the system memory.
18.3.6. MAC function blocks
18.3.6.1. MAC Transmission Block
The Transmission Block takes charge of data transmission. The Transmission Block is compliant with the IEEE 802.3
carrier sense multiple access with collision detection method (CSMA/CD) protocol. This block also supports full duplex
modes that can simultaneously perform transmission and reception. The Transmission Block consists of the following
parts.
For details of the Transmission Block, see 18.3.8 MAC operation.
18.3.6.2. MAC Reception Block
The Reception Block takes charge of data reception. The Reception Block is compliant with the IEEE 802.3 carrier sense
multiple access with collision detection method (CSMA/CD) protocol. This block also supports full duplex modes that can
simultaneously perform transmission and reception. The Reception Block consists of the following parts.
For details on the Reception block, see 18.3.8 MAC operation.
18.3.6.3. Flow Control Block
The Flow Control Block has the following functions:
Rev. 3.1 November 1, 2005
Transmission FIFO, FIFO Control Counter
Preamble, Jam Oscillator
Pad Byte, CRC Generator
Parity Checker
Back Off, Intergap Timer
Reception FIFO, FIFO Control Counter
Address Recognition ARC Block
CRC Generator, Tester
Parity Generator
Recognize MAC control frames the Reception Block received
Transmit MAC control frames (even when the transmitter is paused)
Pause operation timer and counter
Command/Status Register Interface
Options for handing off MAC control frames to the software driver
18-13
Toshiba RISC Processor
TX4939
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