TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 509

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.3.7.1.5. FDCtl field (frame descriptor control)
This item shows the FDCtl field configuration and application. The Transmission queue or Reception queue uses the
COwnsFD bit to synchronize the Ethernet Controller and System process. The Transmission queue or buffer list uses the
FrmOpt field. The Transmission queue or Reception queue uses the BDCount field (the buffer list uses the Frame
Descriptor Length field (FDLength) to enable the use of buffer pools larger than the BDCount field permits). For each
reception packet, an excessive buffer descriptor error is issued when more than 28 buffer descriptors are used.
The Transmission queue uses the FrmOpt field and sets the transmission characteristics of each packet.
You can use combinations of the above bits to set various transmission characteristics. For example, "01110" means
"Little Endian, issue interrupt after transmission, no CRC, no padding for short packets".
In applications such as hubs where transmission packets are being received from both Big Endian and Little Endian
transmission sources, controlling Big Endian for each packet is useful. In computer applications, it is easier to use the
global Big Endian control bit described in 18.4.3.1 DMA Control Register.
Unless you set a global enable bit like that described in 18.4.3.6 Reception Fragment Size Register, the Reception buffer
list uses the option set in the FrmOpt field to control packing and the endian.
When packing is enabled, the RxFragSize Register controls the packing algorithm.
Rev. 3.1 November 1, 2005
Bit(s)
15
14 : 10
4 : 0
COwnsFD
15
10000
01000
00100
00010
10000
00001
Mnemonic
COwnsFD
FrmOpt
BDCount
14
Field Name
Frame Descriptor
Owner
Frame Option
Buffer Descriptor
Count
FrmOpt
10
Description
COwnsFD
1: The Ethernet Controller owns the frame descriptor after the system sets
0: The system owns the frame descriptor after the Ethernet Controller clears
Frame Option
Control option for each frame (see the following description)
BDCount
This is the number of allocated buffer descriptors (1-28).
Big Endian order
Issue interrupt after transmission
Do not add CRC
For short frames, do not add PAD
Big Endian order
Enables packing for this frame's buffer, ignores any global enable bit
the COwnsFD bit.
the COwnsFD bit.
Figure 18-7 FDCtl Field
9
18-17
Reserved
5
4
Toshiba RISC Processor
BD Count
TX4939
0
18
18