TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 514

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.3.8.1.2. Special flow control recipient address
The IEEE802.3 standard specially prescribes a recipient address of 01-80-C2-01-00-01 for PAUSE manipulation packets
to realize full duplex flow control. In order for the MAC to receive packets including the special recipient address for
PAUSE manipulation, you have to set the address in one entry in ARC memory, enable that entry, and then activate ARC
itself.
The details are described in the following paragraphs. However, part of the ARC entry uses the SdPause bit of the
Transmission Control Register and is also used when generating flow control frames.
18.3.8.2. Initializing MAC
After powering up or after performing reset, the MAC Control Status Register is initialized as described in section 18.4
Registers.
The transmission collision count and ARC data is not initialized when you power up or reset the Ethernet Controller. The
transmission collision count is reset when a new packet is transmitted. Initialize ARC memory before enable ARC.
18.3.8.3. MAC Register access
Access to the MAC Register is controlled through the PCI Bus Interface. For details on read access and write access of
the register, including the MAC Control Register, see 18.3.9 DMA operation.
18.3.8.3.1. Clearing special registers
The Lost Packet Error Count Register is cleared when it is read. This makes it possible to synchronize it to software
drivers that tabulate the total error count.
The Transmission Status Register and Reception Status Register are cleared at the beginning of the next packet.
Therefore, values read from the Register Interface may not be stable. These register values are stored in the FDStatus
field of the frame descriptor in memory for each transmission or reception packet. You have to use the software to check
the status value retained in the system data structure.
Rev. 3.1 November 1, 2005
18-22
Toshiba RISC Processor
TX4939
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