TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 516

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
To reduce the statistical probability of similar random number sequences being generated between multiple MACs using
the same random number generator, MAC uses the CRC value of the packet that was previously transmitted successfully
to recalculate a basic random number sequence.
18.3.8.4.4. RMII transmission operation
If there is data to be transmitted, there is no problem with the interpacket gap, and MII preparations are complete (in
other words, there are no collisions for full duplex or for half duplex there are no collisions and there is no CrS),MAC
transmits the preamble and SFD. After that, unless Short Packet transmission is enabled, MAC transmits 64 Bytes of
data regardless of the packet length. If the packet length is less than 64 Bytes, the MAC Transmission Block pads the
LLC Data field with zeroes. If CRC generation is enabled, the MAC Transmission Block appends CRC to the end of the
packet. If a collision occurs during the first 64 Bytes (7-Byte preamble + SFD + 56-Byte frame), the MAC Transmission
Block aborts transmission and transmits a jam pattern (a 32-bit sequence of ones). In this case, it advances the
transmission retry counter by 1, then transfers control to the Back Off State Machine. After the Back Off time elapses, the
MAC Transmission Block tries to resend the packet if there is no problem with the interpacket gap.
If no collisions occur, the MAC Transmission Block transmits the rest of the packet. If the first 64 Bytes are transmitted
without any collision, the MAC Transmission Block provides the DMA engine with permission to overwrite these 64 Bytes.
After transmitting the 64 Bytes, the MAC Transmission Block transmits the reset of the packet and appends CRC to the
end of it. If an underrun occurs in the FIFO or there is a collision that occurs more than 16 times, the MAC Transmission
Block makes no attempt to resend the packet and makes preparations to transmit the next packet registered in the queue.
If a transmission error occurs, the MAC Transmission Block sets the appropriate bit of the Transmission Status Register.
Also, depending on the Transmission Control Register settings, an interrupt may occur.
Figure 18-12 shows the transmission timing of packets with RMII. Tx_en and TxD[1:0] change after the rising edge of
REF_clk, then are stable until sampled at the next rising edge. When in the full duplex transfer mode, CrS and Col
become undefined. When in the half duplex transfer mode, CrS must be asserted after Tx_en and must be asserted
during packet transmission. If CrS is deasserted during packet transmission, a Carrier Lost error will occur. Col retaining
the “L” setting indicates that no collisions have occurred.
Figure 18-13 shows the method the Transmission Block uses to handle collisions. It adds 4-Byte jam data before
deasserting Tx_en. If a collision occurs in the preamble, the jam data is added on after SFD ends.
Rev. 3.1 November 1, 2005
REF_clk
TxD[1:0]
Tx_en
CrS
REF_clk
TxD[1:0]
Col
Tx_en
CrS
Col
Figure 18-13 Transmission when Collision Occurred in the Preamble
Figure 18-12 Transmission with no Collisions
P1
P2
P3
18-24
P4
P5
P6
P7 SFD
J1
J3
Toshiba RISC Processor
J4
TX4939
18
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