TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 517

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.3.8.5. Frame reception procedure
To receive a frame, the Reception Enable bit (RxEn) of the Reception Control Register must be set, and the Reception
Halt Request bit (RxHalt) must be cleared. Furthermore, the Halt Transmission Immediately bit (TxHalt) and the Halt
Request bit (HaltReq) of the MAC Control Register must be cleared. Usually, before setting the above code, the DMA
Controller is initialized by storing a valid address in the Buffer List Form Pointer Register or initializing a Free Descriptor
Area Register and a Free Descriptor Size Register for example. This allows the DMA Reception Controller to control
transfers from the MAC Reception FIFO. For the method of initializing data structures to enable reception, see the
descriptions in subsections 18.3.9 DMA Operation and 18.3.9.5 Receiving frames.
When enabled, the MAC Reception Block always monitors the data stream coming in from RMII. When in the Loop-back
mode, the data stream is inputted from the MAC Transmission Block via RMII.
The MAC Reception Block receives a 0- to 7-Byte preamble and the Start Frame Delimiter (SFD). The MAC Reception
Block checks whether the first nibble received is a preamble, then checks whether there is an SFD in the first 8 Bytes of
the packet. Except for the preamble, the MAC Reception Block treats a packet that does not have the SFD as its first
Byte as a packet fragment and deletes it.
Following after the SFD is the first nibble of the recipient address. The MAC Reception Block generates parity when it
receives 1 Byte of data, then stores it with the data in the MAC Reception FIFO. After that, it signals the existence of
reception data. The MAC Reception Block collects subsequent nibbles into Byte units and stores them in the appropriate
FIFO. The DMA Reception Controller reads them from the MAC Reception FIFO in Byte units, performs a parity check,
and then transfers the data to the DMA Reception buffer. When either the MAC Reception FIFO becomes empty or it
transmits the last Byte of a packet and ends transmission, the MAC Reception Block signals this fact.
If PHY asserts both the Rx_DV and Rx_er signals while receiving a frame, the MAC Reception Block reports that a CRC
error occurred in the current packet.
When the MAC Reception Block receives the recipient address, the ARC tries to recognize the received address. If the
ARC refuses a packet, the MAC Reception Block signals this fact and the DMA Reception Block destroys the data packet.
Rev. 3.1 November 1, 2005
18-25
Toshiba RISC Processor
TX4939
18
18