TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 521

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
Registers for the format of these flags and the counter.
18.3.8.8.1. Transmission error display
Transmission operation ends when an entire packet (preamble, SFD, data, CRC) is transferred to a physical medium
without any collisions occurring. If an internal error or network error occurs, the MAC Transmission Block reports the
content of that error.
If one of the states described below occurs, transmission is aborted and the Status bit is set. After the Status bit is set, an
interrupt occurs if the corresponding Interrupt Enable bit in the Transmission Control Register is set.
Rev. 3.1 November 1, 2005
Error Display
MAC Transmission Parity
Error
MAC Transmission FIFO
Underrun
Carrier Sense Lost
Excessive Collision
Late Collision (Collision
Outside Window)
SQE
Defer
Excessive Deferral
If the MAC encounters a collision during transmission, it backs off, updates the collision counter, and
Description
The data that the DMA Transmission Controller transmits to the MAC Transmission FIFO via DII is
protected by the Parity bit. If a Parity error occurs, the DMA Transmission Controller halts
transmission if the TxParErr bit of the Transmission Status Register is set and interrupts are enabled.
The MAC Transmission FIFO has a capacity of 80 Bytes so even if a collision occurs, it holds 64
Bytes for retransmission and can support DMA latency up to 1.28 µs (128-bit late time=16-Byte time).
The DMA Transmission Controller has sufficient bandwidth, so if an underrun occurs in the MAC
Transmission FIFO, this usually indicates that there is a problem with the latency of the PCI Bus.
When such an underrun occurs, the Underrun bit of the Transmission Status Register is set.
Carrier Sense (CrS) is monitored from the beginning of the Start Frame Delimiter to the last
transmission Byte. This error indicates that transmission was not aborted even though CrS either
does not exist or was lost due to a network fault or other cause. When in the Loop-back mode, Tx_en
drives CrS. With full duplex transfers, Carrier Sense Lost is not asserted since CrS is not handed off
to the Transmission Block. When Carrier Sense is lost, the LostCrS bit of the Transmission Status
Register is set.
then tries to retransmit the data after a specific time interval elapses. When the counter becomes “16”,
transmission is aborted if transmission is attempted 16 times and a collision occurred every time. A
network fault could cause excessive collisions. When excessive collisions occur, the ExColl bit of the
Transmission Status Register is set.
When the network is operating properly, the MAC detects a collision in the first 64 Bytes of the
transmitted data. When a collision occurs after this time elapses (when one occurs outside the
window), this means that there is a network fault. In this case, the LateColl bit of the Transmission
Status Register is set and packet transmission is aborted. In other words, transmission is not retried
after a late collision occurs.
When in the 10 Mbps mode, “heartbeat” is checked at the end of the transmitted packet. A heartbeat
is a short collision signal that occurs within the first 40-bit late time period after the transmission ends.
When a heartbeat is not detected, the SQErr bit of the Transmission Status Register is set.
This state indicates that it is necessary to defer transmission since the transmission route was already
in use when packet transmission was attempted. This is not an error, but unless an error occurs, this
state is used to indicate the state of the transmission route. When the Defer state occurs, the TxDefer
bit of the Transmission Status Register is set.
There are cases where it is necessary to defer transmission since the transmission route was already
in use when the MAC attempted to transmit a packet the first time. If the deferral time is longer than
MAX_DEFERRAL (2.4288 ms when in the 10 Mbps mode, 0.24288 ms when in the 100 Mbps mode)
and the NoExDef bit of the Transmission Control Register is disabled, then the ExDefer bit of the
Transmission Status Register is set. When the Excessive Deferral state occurs, transmission is not
aborted, but a network fault may have occurred. It is possible to transmit an Excessive Deferral
interrupt before packet transmission is complete and display it in the IntExDefer bit of the Interrupt
Factor Register.
Table 18-5 Transmission Error Display (1/2)
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Toshiba RISC Processor
TX4939
18
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