TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 522

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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EMAC
18.3.8.8.2. Reception error display
After detecting the Start Frame Delimiter (SFD), the MAC writes the data received from the physical medium to the MAC
Reception FIFO. The MAC Reception Block checks whether an overflow occurred in the MAC Reception FIFO during
reception. Also, when reception ends, it checks for external errors (Alignment, CRC, Maximum Frame Length Exceeded).
18.3.8.9. Accessing station management data
Following is the basic sequence of events when accessing station management data.
Rev. 3.1 November 1, 2005
Error Display
MAC Reception Parity
Error
Alignment Error
CRC Error
Overflow Error
Maximum Frame Length
Exceeded Error
MII Error
The system software checks the Busy bit and confirms that MD is not Busy.
For a write operation, you have to write data to the Data Register before setting up the Control Register.
The software writes the MDC address, the Read or Write flag, and sets the Busy bit.
The Ethernet Controller ends operation then clears the Busy bit.
In the case of a read operation, the system software can read the Data Register after it detects that the Busy bit
was cleared.
Description
Once data enters the MAC Reception FIFO, it is protected by the Parity bit. If the RxParErr bit of the
Reception Status Register is set and interrupts are enabled when a Parity error occurs, the MAC
Reception Block aborts reception.
After reception ends, the MAC Reception Block checks whether reception packets are properly
framed at the 8-bit boundaries. If they are not properly framed and CRC is invalid, the data is
corrupted as it passes along the network and the MAC Reception Block signals an Alignment error.
The MAC Reception Block also signals a CRC error at this time. The AlignErr bit and CRCErr bit of
the Reception Status Register are set.
After reception ends, if the MAC Reception Block checks CRC and there was an error, it signals that
error. The CRC error, Frame Alignment error, and the Maximum Frame Length Exceeded error are
network errors that the Reception Block detects. These errors could be detected in the following
combinations.
During reception, the data is first stored in the MAC Reception FIFO, and then is transferred to the
DMA Reception Controller. If the MAC Reception FIFO becomes full due to a cause such as
excessive system latency, then the MAC Reception Block sets the Overflow bit of the Reception
Status Register.
The MAC Reception Block checks the packet length when reception ends. If it receives a frame that is
longer than the maximum frame length of 1518 Bytes when the Long Frame mode is not enabled, the
MAC Reception Block signals this error.
When PHY detects a media error such as a coding violation, it signals MAC by asserting Rx_er. When
MAC acknowledges the assertion of Rx_er, it deletes the received packet. A CRC error is forcibly
issued and reception of the packet is terminated. There are also cases where an Alignment error or
Minimum Frame Length error are detected.
- CRC error only
- Alignment error and CRC error only
- Maximum Frame Length Exceeded error and CRC error only
- Alignment error, Maximum Frame Length Exceeded error, and CRC error
Table 18-6 Reception Error Display
18-30
Toshiba RISC Processor
TX4939
18
18

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