TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 524

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.3.9.2. Initial setup of DMA and MAC
After initially setting up the PCI, the DMA Control Register and MAC Control Register are usually mapped to an I/O
address space or memory address space and are available for reading and writing.
Registers such as the following require initial setup.
There are also situations where the following registers require initial setup.
18.3.9.3. Initializing the queues
The system has to set up the transmission queue, buffer list, and reception descriptor area before starting up the
Ethernet Controller.
18.3.9.3.1. Initializing the transmission queue
The Transmission Block has two operation modes: Batch Processing and Continuous Polling. When in the Batch
Processing mode, the system software prepares a link list of the frame descriptors to be transmitted. The final descriptor
must have "1" set in the EOL (end of list) field. When the last frame descriptor is transmitted, the Transmission Frame
Pointer Register reads EOL and transmission ends. To resume transmission after this, the system resets the
Transmission Frame Pointer Register.
When in the Continuous Polling mode, the system software also prepares a link list of the frame descriptors to be
transmitted. However, the last frame descriptor is a dummy frame descriptor. The beginning of a link list is only a dummy
frame descriptor, so it is okay for it to be empty. The system owns the dummy descriptor to prevent the Ethernet
Controller from accessing it. Transmitting a new packet overwrites the dummy frame descriptor. This is explained in
18.4.4 Flow Control Register group.
18.3.9.3.2. Initializing the buffer list
The buffer list queue is either a single frame descriptor or multiple frame descriptors combined into a link list containing a
list of the empty buffer descriptors that is initialized. It is okay for the buffer list to have one of the following configurations.
In configurations 1 and 2 above, the EOL bit of the FDNext field is set while in configuration 3, the FDNext field of the last
frame descriptor points to the first frame descriptor. You can use the Reception Buffer Fragment Size Register to globally
pack a buffer. Also, you can use the Control field (FDCtl) of a frame descriptor to select whether to pack in buffer area
units. Setting up the Buffer ID field when packing a buffer is useful in managing memory. For details on packing buffers,
Rev. 3.1 November 1, 2005
DMA Transmission Frame Pointer: To start transmission
DMA Buffer List Frame Pointer: To provide buffer for receiving data
DMA Free Descriptor Area Base Register or DMA Free Descriptor Area Size Register: To initialize the reception
signaling area
DMA Transmission Polling Control Register: To customize polling of transmission packets
DMA Transmission Threshold Register: To customize transmission latency handling
MAC Transmission Control Register: To change the default transmission settings
MAC Reception Control Register: To change the default reception settings
MAC ARC Control Register: To customize the recognition conditions of station addresses and multicast
addresses
MAC ARC Address Register and MAC ARC Data Register: To set the filtering of station addresses and other
addresses
MAC ARC Enable Register: To enable each ARC entry after setting up the ARC
MAC Control Register: To customize the MAC configuration
DMA Transmission Control Register: To customize the Burst size
1. One frame descriptor containing many free buffer descriptors
2. A link list of frame descriptors
3. Wrap-around queue in which the last frame descriptor points to the first frame descriptor
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Toshiba RISC Processor
TX4939
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