TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 532

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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EMAC
18.4.2.4. PCI Status Register (PCI_Stat) 0x06
Software reset initializes the PCI Status Register to 0x0230.
The PCI Status Register retains status information on events relating to the PCI Bus. There are several points about this
register that you should keep in mind. First, writing "1" to a bit in this register clears it to "0". Also, the value of each bit
does not change when you write "0" to it. This enables the system and PCI device to simultaneously update the status
information. For details, see Subsection 6.2.3 Device Status of the PCI 2.2 specification.
Rev. 3.1 November 1, 2005
Default
Default
Bit(s)
15
14
13
12
11
10 : 9
8
7
6
5
4
3 : 0
Name
Name
TYPE
TYPE
DParErr SSysErr RMasAbt RTarAbt STarAbt
R/W1C
31
15
0
Mnemonic
DParErr
SSysErr
RMasAbt
RTarAbt
STarAbt
DEVSEL
DParD
FastCap
UDF
Cap66
ExCap
R/W1C
30
14
0
R/W1C
29
13
0
Field Name
Detected Parity Error
Signal System Error
Receive Master Abort
Receive Target Abort
Signal Target Abort
Device Select Timing
Detect Data Parity Error
Fast Back-to-back Capable
User Defined Function
66 MHz Operation Capable
Extended Function
Reserved
R/W1C
28
12
0
R/W1C
27
11
0
Figure 18-22 PCI Status Register
26
10
DEVSEL
0
R
25
9
1
18-40
DParD FastCap UDF Cap66 ExCap
R/W1C
RESERVED
24
Description
DParErr (Default: 0, R/W)
Indicates that a parity error was detected. This bit is set if a
parity error is detected even when the register's Parity Error
Response bit is not set. This also applies to parity errors
occurring during an address cycle.
SSysErr (Default: 0, R/W)
This bit is set when the device asserts SERR#.
RMasAbt (Default: 0, R/W)
Indicates that the current device is the Bus Master and that
Master Abort ended the Bus Master transaction (excluding
special cycles).
RTarAbt (Default: 0, R/W)
Indicates that the current device is the Bus Master and that
Target Abort ended the Bus Master transaction.
STarAbt (Default: 0, R/W)
Indicates the current device is the target and that Target Abort
ended the Bus Master transaction.
DEVSEL (Fixed to "01", R)
The latest output timing of DEVSEL# when the Ethernet
Controller is accessed as the target device is "medium speed".
This field is encoded as follows.
00:
01:
10:
DParD (Default: 0, R/W)
This bit is set when all of the three following conditions are met.
PERR# was asserted as the Bus Master, but the target
asserted it.
The agent that set PERR# was the Bus Master.
The Parity Error Response bit of the PCI Control Register is set
to "1".
FastCap (fixed to "0", R)
The Ethernet Controller cannot perform consecutive
transactions from different agents.
UDF (fixed to "0", R)
Indicates that there are no user-defined functions in the
Ethernet Controller.
Cap66 (fixed to "1", R)
Indicates that the Ethernet Controller can operate at 33-66
MHz.
ExCap (fixed to "1", R)
Indicates that the Ethernet Controller has extended functions.
8
0
23
R
0
7
Fast
Medium Speed
Slow
22
R
6
0
21
R
5
1
20
R
1
4
Toshiba RISC Processor
19
3
RESERVED
18
2
17
1
TX4939
16
0
18
18

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