TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 539

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.4.3. DMA Control, Status Register group
The DMA engine and system software jointly manage three queues: the transmission queue, the reception queue, and
the buffer list. The transmission queue is used for frame descriptors that are ready for transmission and are standing by.
The reception queue is used for frame descriptors that have been received and are waiting for processing by the system
software. The buffer list is a buffer descriptor queue. Buffer descriptors describe system memory areas that can be used
to store reception data. The free descriptor area (FDA) is a memory area that the Ethernet Controller can write
transmission queue frame descriptors and buffer list descriptors to.
Rev. 3.1 November 1, 2005
18-47
Toshiba RISC Processor
TX4939
18
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