TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 546

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.4.3.6. Reception Fragment Size Register (RxFragSize)
Hardware resets initialize the Reception Fragment Size Register to 0x0000_0000. Software resets do not change the
register contents.
The Reception Fragment Size Register specifies the size of minimum data fragments that the Ethernet Controller
generates. The minimum fragment size must be a multiple of 4. Therefore, the lower 2 bits are always “0”. You can use
the EnPack bit to globally enable packing, or you can enable packing in buffer-area units. For more information on the
enabling of packing in buffer-area units, see the description in 18.3.7.1.5 FDCtl field (frame descriptor control).
The Ethernet Controller always stores reception data in addresses aligned to 4-Byte boundaries. Therefore, the last 1-3
bytes of a frame may be unused.
When enabling packing, the MinFrag value must be greater than 0 for the Ethernet Controller to function properly. When
using packing, use a software driver to set the MinFrag field and EnPack bit.
When not enabling packing, the MinFrag value must remain at “0”.
Packing is performed when more than the Minimum Fragment Size + 4 Bytes in the buffer is free. Packing is not
performed when the amount of free space in the buffer is less than the Minimum Fragment Size. In this case, data is
stored starting from the next buffer.
Rev. 3.1 November 1, 2005
Bit(s)
31 : 16
15
14 : 12
11 : 2
1 : 0
Default
Default
Name
Name
TYPE
TYPE
EnPack
R/W
31
15
Mnemonic
EnPack
MinFrag
0
30
14
RESERVED
29
13
Field Name
Reserved
Enable Packing
Reserved
Minimum Fragments
Reserved
28
12
Figure 18-38 Reception Fragment Size Register
27
11
26
10
25
9
18-54
RESERVED
Description
EnPack (Default: 0, R/W)
1: Uses the MinFrag value for buffer packing control.
0: Uses the FDCtl field of the frame descriptor for buffer
MinFrag (Default: 0x000, R/W)
The minimum byte count when partially writing to a buffer that
contains data.
24
8
packing control.
23
7
MinFrag
0x000
R/W
22
6
21
0x14
5
20
4
Toshiba RISC Processor
19
3
18
2
RESERVED
17
1
TX4939
16
0
18
18